發(fā)布時間：2018-04-23 10:19

  本文選題：24位Sigma-delta模數(shù)轉(zhuǎn)換器 + Sigma-delta調(diào)制器�。� 參考：《西安電子科技大學》2015年碩士論文

【摘要】：本文開展了24位Sigma-delta ADC中降采樣數(shù)字濾波器的研究與設計,研究工作從Sigma-delta調(diào)制器結(jié)構(gòu)入手,通過ASIC數(shù)字電路設計流程完成一款輸入信號256MHz輸出1MHz位寬24的降采樣數(shù)字濾波器,本文的主要工作內(nèi)容有:1.Sigma-Delta ADC的基本原理和結(jié)構(gòu)的研究。簡單討論了ADC的原理和結(jié)構(gòu),然后重點闡述Sigma-Delta ADC的工作原理、實現(xiàn)結(jié)構(gòu)、關鍵技術(shù)以及性能指標。2.Sigma-delta ADC的基本原理結(jié)構(gòu)和性能仿真分析。使用Matlab搭建四級單環(huán)1位CIFB(Cascade-of-Integrator-Feed-Back)結(jié)構(gòu)的Sigma-delta調(diào)制器,根據(jù)ADC系統(tǒng)設計要求確定結(jié)構(gòu)參數(shù)后,進行了系統(tǒng)仿真,調(diào)制器的輸入頻率為256MHz,過采樣率為256,信噪比為123.5dB,精度達到了20.22bits。3.降采樣數(shù)字濾波器基本原理與結(jié)構(gòu)的設計研究。首先討論了降采樣數(shù)字濾波器的原理結(jié)構(gòu),然后根據(jù)原理分析設計一款24bit的降采樣數(shù)字濾波器,采用三級級聯(lián)結(jié)構(gòu),第一級為CIC抽取濾波器,用來實現(xiàn)主要信號抽取功能;第二級為CIC補償濾波器,用來補償CIC抽取濾波器的通帶衰減,同時對信號實現(xiàn)2倍抽取;第三級為兩個半帶濾波器級聯(lián),用來調(diào)整濾波器的阻帶衰減和過渡帶帶寬,同時也對信號實現(xiàn)4倍抽取。4.降采樣數(shù)字濾波器的系統(tǒng)設計和仿真。輸入信號頻率256MHz,輸出頻率為1MHz,抽取倍數(shù)為256,采用Matlab中的Simulink工具建立降采樣濾波器各級子模塊并封裝,對各級和系統(tǒng)分別進行仿真。5.降采樣數(shù)字濾波器的ASIC實現(xiàn)。編寫降采樣數(shù)字濾波器的RTL代碼和測試平臺代碼,在Modelsim中進行功能仿真,驗證功能正確后,通過DC對代碼進行邏輯綜合得到門級網(wǎng)表,查看時序報告建立時間滿足后將網(wǎng)表導入ICC中進行物理實現(xiàn),實現(xiàn)過程包括Floorplan(布圖規(guī)劃)、Placement(標準單元擺放)、CTS(時鐘樹綜合)、Route(繞線),繞線完畢之后通過Starrcc抽取寄生參數(shù)在PT中進行靜態(tài)時序分析,保持時間都滿足之后添加DFM的相關設置,保存得到降采樣數(shù)字濾波器的GDS格式版圖,在Carlibre中通過了DRC和LVS檢查。本文的工作對高精度Sigma-delta ADC中的降采樣數(shù)字濾波器的設計具有一定的借鑒意義。
[Abstract]:In this paper, the research and design of down-sampling digital filter in 24-bit Sigma-delta ADC is carried out. Starting with the structure of Sigma-delta modulator, a downsampling digital filter with input signal 256MHz output 1MHz bit width 24 is completed by ASIC digital circuit design flow. The main work of this paper is: 1. The basic principle and structure of Sigma-Delta ADC. This paper briefly discusses the principle and structure of ADC, and then focuses on the working principle, implementation structure, key technology and basic principle structure and performance simulation analysis of Sigma-Delta ADC. 2. Sigma-delta ADC. A four-stage single-ring Sigma-delta modulator with one bit CIFBN Cascade-of-Integrator-Feed-Back-structure is constructed by using Matlab. After determining the structural parameters according to the design requirements of the ADC system, the system simulation is carried out. The input frequency of the modulator is 256 MHz, the over-sampling rate is 256, the signal-to-noise ratio is 123.5 dB, and the precision is 20.22 bits.3. Design and Research on the basic principle and structure of De-sampling Digital filter. Firstly, the principle structure of demultiplexing digital filter is discussed, and then a demultiplexing digital filter of 24bit is designed according to the principle. It adopts three-stage cascade structure, the first stage is CIC decimation filter, which is used to realize the main signal decimation function. The second stage is a CIC compensation filter, which is used to compensate the passband attenuation of the CIC decimation filter, and the signal is decimated twice. The third stage is a cascade of two half-band filters, which is used to adjust the stopband attenuation and the transition band bandwidth of the filter. At the same time, the signal is 4 times decimated. System design and simulation of decimation digital filter. The input signal frequency is 256 MHz, the output frequency is 1 MHz, and the decimation multiple is 256. The down-sampling filter sub-modules are established and encapsulated by the Simulink tool in Matlab. ASIC implementation of decimated digital filter. The RTL code and the test platform code of the down-sampling digital filter are written, and the function simulation is carried out in Modelsim. After the function is verified correctly, the gate network table is obtained by logic synthesis of the code by DC. After viewing the time sequence report setup time is satisfied, the network table is imported into ICC for physical implementation. The implementation process includes the design of Starrcc (layout Planning) (CTS). After winding, the parasitic parameters are extracted by Starrcc to analyze the static time sequence in PT, and the relative setting of DFM is added after the holding time is satisfied. The GDS format layout of the decimated digital filter is saved, and the DRC and LVS are checked in Carlibre. The work in this paper can be used for reference in the design of decimated digital filter in high precision Sigma-delta ADC.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN713.7

【參考文獻】

相關期刊論文 前5條

1 李迪;楊銀堂;朱樟明;石立春;吳笑峰;王江安;;Improved low-distortion sigma-delta ADC with DWA for WLAN standards[J];半導體學報;2010年02期

2 李迪;楊銀堂;石立春;吳笑峰;;Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology[J];半導體學報;2009年10期

3 馬紹宇;韓雁;黃小偉;楊立吾;;一種高性能、低功耗音頻ΣΔ調(diào)制器[J];半導體學報;2008年10期

4 朱樟明;李亞妮;楊銀堂;;一種1.8V 10位120MS/s CMOS電流舵D/A轉(zhuǎn)換器IP核[J];半導體學報;2008年03期

5 褚煒路;戎蒙恬;李萍;劉文江;;二階多比特Sigma-Delta ADC中的自適應量化算法[J];上海交通大學學報;2008年02期

相關博士學位論文 前3條

1 曹桂平;高精度Sigma-Delta調(diào)制器研究及ASIC實現(xiàn)[D];中國科學技術(shù)大學;2012年

2 李迪;高性能sigma-delta ADC的設計與研究[D];西安電子科技大學;2010年

3 易婷;高性能∑△模數(shù)轉(zhuǎn)換器設計[D];復旦大學;2002年

相關碩士學位論文 前7條

1 張永來;18位精度音頻Sigma-Delta ADC設計[D];哈爾濱工業(yè)大學;2013年

2 李靖;一種低速高精度Sigma-Delta調(diào)制器的研究與設計[D];吉林大學;2013年

3 陳麗;應用于Sigma-Delta ADC中數(shù)字抽取濾波器的設計[D];吉林大學;2012年

4 吳倩瑜;一種Sigma-Delta ADC中抽取濾波器的研究[D];重慶大學;2010年

5 余曉帆;Sigma-Delta模數(shù)轉(zhuǎn)換器中數(shù)字抽取濾波器的設計與ASIC實現(xiàn)[D];電子科技大學;2010年

6 王其超;一種16位音頻Sigma-Delta模數(shù)轉(zhuǎn)換器的研究與設計[D];西安電子科技大學;2009年

7 蔡友;Sigma-Delta ADC中抽取濾波器的研究與實現(xiàn)[D];浙江大學;2007年

，

本文編號：1791538