發(fā)布時(shí)間：2018-04-23 04:42

  本文選題：DDS + PLL��； 參考：《南京理工大學(xué)》2015年碩士論文

【摘要】：隨著通信系統(tǒng)技術(shù)的不斷向前進(jìn)步,系統(tǒng)對(duì)頻率源的準(zhǔn)確度、穩(wěn)定度以及頻譜的純度有了更高的要求,單一的頻率合成技術(shù)已經(jīng)很難滿足設(shè)計(jì)的需要。鎖相頻率合成已經(jīng)是一項(xiàng)很成熟的技術(shù),它具有輸出頻率高和雜散抑制度好的特點(diǎn)。DDS技術(shù)雖然有著低相位噪聲和頻率分辨率高的優(yōu)勢(shì),然而雜散抑制較差以及輸出頻率較低。本課題設(shè)計(jì)的目的正是將兩種頻率合成技術(shù)各自的優(yōu)點(diǎn)結(jié)合起來,從而設(shè)計(jì)出高性能的Ka波段小頻率步進(jìn)寬帶頻率源。論文在對(duì)DDS與PLL理論分析的基礎(chǔ)上,討論了DDS+PLL技術(shù)相結(jié)合使用的幾種方案,并且分析了每一種方案的優(yōu)缺點(diǎn)。然后結(jié)合論文指標(biāo)的具體要求,選擇了一種適合的方案,并在該方案的基礎(chǔ)上,進(jìn)行芯片的選型與指標(biāo)符合性分析。最后是硬件電路的設(shè)計(jì)與調(diào)試,電路在結(jié)構(gòu)方面運(yùn)用分腔模塊化設(shè)計(jì),既簡化了整個(gè)電路設(shè)計(jì)的復(fù)雜性,又使電路調(diào)試變得方便。電路在設(shè)計(jì)方面采用DDS直接激勵(lì)PLL的合成方案,研制了Ka波段(27GHz-30GHz)小步進(jìn)寬帶頻率源。經(jīng)過調(diào)試后,頻率源能在該頻段內(nèi)實(shí)現(xiàn)10kHz頻率間隔的任意輸出；相噪達(dá)到了-52dBc/Hz@10Hz、-63dBc/Hz@100Hz、-72.8dBc/Hz @1kHz、-80.7dBc/Hz@10kHz、-90.1dBc/Hz @100kHz；雜散抑制度達(dá)到68dBc；輸出功率不小于11.8dBm,符合設(shè)計(jì)指標(biāo)。
[Abstract]:With the continuous progress of communication system technology, the system has higher requirements for the accuracy, stability and spectrum purity of the frequency source. The single frequency synthesis technology has been difficult to meet the needs of the design. Phase locked frequency synthesis has been a very mature technology, which has the characteristics of high output frequency and good stray suppressor system.DD. Although the S technology has the advantages of low phase noise and high frequency resolution, the stray suppression is poor and the output frequency is low. The purpose of this project is to combine the advantages of the two frequency syntheses, and then design a high performance Ka band small frequency step wideband frequency source. The thesis is based on the theoretical analysis of DDS and PLL. On the basis of this, several schemes of DDS+PLL technology are discussed, and the merits and demerits of each scheme are analyzed. Then a suitable scheme is chosen according to the specific requirements of the paper index. On the basis of this scheme, the selection of the chip and the conformity analysis of the index are carried out. Finally, the design and debugging of the hardware circuit and the electricity are made. The modular design of the split cavity is used in the structure, which not only simplifies the complexity of the whole circuit design, but also makes the circuit debugging easier. In the design of the circuit, the DDS direct excitation PLL synthesis scheme is adopted in the design, and the Ka band (27GHz-30GHz) small step broadband frequency source is developed. After the commissioning, the frequency source can realize the 10kHz frequency within the frequency band. Arbitrary output of the septum; phase noise reached -52dBc/Hz@10Hz, -63dBc/Hz@100Hz, -72.8dBc/Hz @1kHz, -80.7dBc/Hz@10kHz, -90.1dBc/Hz @100kHz; the stray suppression system reached 68dBc; the output power was not less than 11.8dBm, which accorded with the design index.

【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN741

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前4條

1 梁木生;Ka波段頻率合成器研究[D];電子科技大學(xué);2008年

2 王晨;基于DDS的信號(hào)產(chǎn)生技術(shù)研究[D];西安電子科技大學(xué);2010年

3 張蕭;微波DDS頻率源技術(shù)研究[D];電子科技大學(xué);2013年

4 陳鑫;基于DDS和PLL的寬帶YTO頻率綜合器設(shè)計(jì)與實(shí)現(xiàn)[D];電子科技大學(xué);2013年

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本文編號(hào)：1790528