發(fā)布時間：2018-04-21 23:39

  本文選題：功率MOSFET + 邊端設計�。� 參考：《西南交通大學》2015年碩士論文

【摘要】：功率半導體器件是電力電子技術發(fā)展的基礎,功率MOSFET由于其具有高輸入阻抗、低驅動功率、高開關速度、優(yōu)越的頻率特性以及良好的熱穩(wěn)定性等特點,自最初誕生以來,其結構和性能得到了迅速的發(fā)展。功率MOSFET的發(fā)展趨勢是持續(xù)縮小芯片內單位元胞面積與邊端尺寸,因為更小的面積意味著更大的溝道密度和更低的導通電阻,或者在相同的導通電阻下可以獲得更小的芯片面積,進而降低成本,而更短的邊端尺寸同樣意味著在芯片面積不變的情況下更多的元胞容納數(shù)目,更低的導通電阻。功率MOSFET的主要設計矛盾是保證擊穿電壓(Breakdown Voltage,BV)和芯片面積的前提下,盡可能的降低器件的導通電阻Rds(on),這也成為當今功率MOSFET技術發(fā)展的主要方向。本論文的主要研究內容是功率器件的耐壓優(yōu)化設計,首先研究功率器件本身的擊穿機制；然后研究功率器件芯片的邊端保護結構以及優(yōu)化,這一部分包括了傳統(tǒng)結構下場板場環(huán)的復合應用模型以及通過擴散濃度的控制而實現(xiàn)的橫向變摻雜模型。具體研究內容如下：(1)垂直功率器件的重要參數(shù)組成,其中耐壓是功率器件的關鍵參數(shù)之一,通過理論與仿真研究了垂直功率器件的設計與其耐壓之間的相互影響。(2)普遍工藝下為了實現(xiàn)電場在芯片邊端處的收斂,通常采用場板與場環(huán)的復合使用,文章通過場板場環(huán)設計中的關鍵參數(shù)研究,在較小占用芯片面積的情況下實現(xiàn)了高耐壓。(3)為了在更短的邊端長度下實現(xiàn)同樣水平甚至更高的耐壓,本文討論了通過控制邊端摻雜濃度實現(xiàn)的高電場強度承受能力的邊端技術,通過理論與仿真討論了該種設計下的關鍵參數(shù)以及實際耐壓水平。
[Abstract]:Power semiconductor devices are the basis of the development of power electronics technology. Power MOSFET, because of its high input impedance, low driving power, high switching speed, superior frequency characteristics and good thermal stability, has been born since the beginning. Its structure and properties have been developed rapidly. The trend of power MOSFET is to continuously reduce the cell area and the side end size of the chip, because smaller area means greater channel density and lower on-resistance, or smaller chip area can be obtained under the same on-resistance. This in turn reduces costs, while shorter end sizes also mean more cell accommodations and lower on-resistance when the size of the chip remains the same. The main design contradiction of power MOSFET is to ensure breakdown voltage Breakdown voltage BV) and chip area, and to reduce the on-resistance of the device as much as possible, which has become the main direction of the development of power MOSFET technology. The main content of this thesis is the design of the power device. Firstly, the breakdown mechanism of the power device itself is studied, then the side protection structure and the optimization of the power device chip are studied. This part includes the composite application model of the field ring of the traditional structure and the transversely variable doping model realized by the control of diffusion concentration. The specific contents of the study are as follows: (1) the important parameters of the vertical power device, among which the voltage withstand is one of the key parameters of the power device. In order to realize the convergence of electric field at the edge end of the chip, the composite use of the field plate and the field loop is usually adopted in order to realize the convergence of the electric field at the edge of the chip under the universal process of the design of vertical power device and the interaction between its voltage and voltage. Through the research of the key parameters in the design of the field plate ring, a high voltage withstanding is realized in the case of less chip area. (3) in order to achieve the same level or higher voltage under the shorter side end length, In this paper, the edge-end technology of high electric field strength bearing capacity by controlling the edge-end doping concentration is discussed, and the key parameters and the actual voltage withstand level of the design are discussed through theory and simulation.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386

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本文編號：1784663