本文選題：TSV + 熱應(yīng)力�。� 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：在二維集成電路中,互連金屬層的增加限制了電路的性能。而利用垂直互連技術(shù)來實(shí)現(xiàn)多層芯片堆疊的三維集成電路(Three-Dimension-Integrated-Circuit,3D IC)在很多方面都就有優(yōu)勢,主要包括:縮短互連線的長度、降低功耗以及允許異質(zhì)集成等等。實(shí)現(xiàn)垂直互連的最有效的方式是硅通孔(Through-Silicon-Via,TSV)技術(shù),但TSV結(jié)構(gòu)會引入許多問題,尤其在熱機(jī)械可靠性方面。同時(shí),TSV引起的熱應(yīng)力問題又會造成器件性能的變化。因此本文主要討論了TSV熱應(yīng)力對于載流子遷移率、器件閾值電壓以及飽和電流變化的影響,并得到了以下結(jié)論:(1)創(chuàng)建了提取TSV熱應(yīng)力的數(shù)學(xué)模型。利用彈性力學(xué)基本理論,尤其是平面應(yīng)變問題以及平面軸對稱結(jié)構(gòu)問題,然后利用具體的TSV結(jié)構(gòu)列出求解未知系數(shù)的邊界條件,從而創(chuàng)建了提取TSV熱應(yīng)力的數(shù)學(xué)模型。(2)利用多種類型的TSV來進(jìn)行驗(yàn)證。本文針對多種類型的TSV結(jié)構(gòu)進(jìn)行仿真,即傳統(tǒng)的圓柱形TSV結(jié)構(gòu)、環(huán)形TSV結(jié)構(gòu)以及較為復(fù)雜的同軸TSV結(jié)構(gòu)。把從熱應(yīng)力模型中得到的應(yīng)力數(shù)據(jù)與仿真得到的應(yīng)力數(shù)據(jù)放在同一個(gè)坐標(biāo)系中進(jìn)行驗(yàn)證,并對驗(yàn)證過的應(yīng)力進(jìn)行坐標(biāo)系的轉(zhuǎn)換。(3)不同溝道下的載流子遷移率的變化。本文討論了不同溝道方向條件下的遷移率的變化情況,即[100]晶向和[110]晶向。當(dāng)溝道方向?yàn)閇100]晶向時(shí),電子遷移率變化較大。而且在坐標(biāo)軸方向變化較大,在兩條坐標(biāo)軸之間的區(qū)域變化較小。但當(dāng)溝道方向?yàn)閇110]晶向時(shí),空穴遷移率變化較大。而且在兩條坐標(biāo)軸之間的區(qū)域變化較大,在坐標(biāo)軸方向變化較小。同時(shí)根據(jù)相應(yīng)的載流子遷移率變化情況,對器件的放置方式進(jìn)行了討論。(4)器件閾值電壓的變化。TSV熱應(yīng)力還會引起器件閾值電壓的變化,TSV熱應(yīng)力會使得器件閾值電壓降低。其中P型金屬氧化物半導(dǎo)體(P-Type-Metal-Oxide-Semiconductor,NMOS)器件的閾值電壓最大減少量為32mV,N型金屬氧化物半導(dǎo)體(N-Type-Metal-Oxide-Semiconductor,PMOS)器件的閾值電壓最大減少量為50mV。(5)器件飽和電流的變化。TSV引起的熱應(yīng)力會造成器件載流子遷移率和器件閾值電壓的變化,進(jìn)而會引起器件飽和電流的影響。NMOS器件的飽和電流在整個(gè)坐標(biāo)系均為增加的,并且最大的變化率超過了14%。同時(shí)NMOS器件的飽和電流在X軸方向增加較多,在Y軸方向上變化較小,這與只考慮遷移率變化的情況不同。PMOS器件的飽和電流變化更大,而且飽和電流在Y軸方向上增加較大,在X軸方向上減少。(6)TSV物理參數(shù)的影響。TSV結(jié)構(gòu)的物理參數(shù)也會對器件的飽和電流產(chǎn)生影響,其中較小的TSV半徑以及較大的絕緣層厚度可以對器件飽和電流的變化產(chǎn)生積極的作用。而且金屬Cu和SiO2材料的組合下的飽和電流變化最大,接著是金屬Cu和BCB材料的組合,然后是金屬W和BCB材料的組合,最后是金屬W和SiO2材料的組合。
[Abstract]:In two-dimensional integrated circuits, the increase of interconnect metal layers limits the circuit performance.Three-dimensional Integrated Circuit 3D ICs using vertical interconnection technology to realize multilayer chip stacking has advantages in many aspects, such as shortening the length of interconnection lines, reducing power consumption and allowing heterogeneous integration, and so on.The most effective way to realize vertical interconnection is the Through-Silicon-Viav technology, but the TSV structure will introduce many problems, especially in the aspect of thermal mechanical reliability.At the same time, the thermal stress caused by TSV will change the performance of the device.Therefore, the influence of TSV thermal stress on carrier mobility, device threshold voltage and saturation current is discussed in this paper, and the following conclusion is drawn: 1) A mathematical model for extracting TSV thermal stress is established.By using the basic theory of elasticity, especially the plane strain problem and the plane axisymmetric structure problem, the boundary conditions for solving the unknown coefficients are listed by using the concrete TSV structure.Thus a mathematical model for extracting TSV thermal stress is established. The model is verified by using various types of TSV.In this paper, many kinds of TSV structures are simulated, that is, the traditional cylindrical TSV structure, the ring TSV structure and the more complex coaxial TSV structure.The stress data obtained from the thermal stress model and the stress data obtained from the simulation are verified in the same coordinate system, and the verified stress is transformed into a coordinate system.In this paper, we discuss the change of mobility under different channel directions, that is, [100] direction and [110] direction.When the channel direction is [100], the electron mobility varies greatly.Moreover, there is a great change in the direction of the coordinate axis and a small change in the region between the two axes.However, when the channel direction is [110], the hole mobility varies greatly.Moreover, the region between the two axes varies greatly, and the change is small in the axis direction.At the same time, according to the change of carrier mobility, the device placement mode is discussed. The change of the threshold voltage. TSV thermal stress will also cause the change of the device threshold voltage. The TSV thermal stress will reduce the device threshold voltage.The maximum reduction of threshold voltage of P-Type-Metal-Oxide-Semiconductor NMOSs is the maximum reduction of the threshold voltage of 32mV / N type metal oxide semiconductor devices N-Type-Metal-Oxide-Semiconductor PMOSs. The maximum reduction of threshold voltage is 50mV.5. the thermal stress caused by TSV is caused by the change of saturation current.Changes in carrier mobility and threshold voltage of devices,The saturation current of NMOS devices is increased in the whole coordinate system, and the maximum change rate is more than 14.At the same time, the saturation current of the NMOS device increases more in the X axis direction and changes slightly in the Y axis direction, which is different from the case of considering the mobility change only. The saturation current of the NMOS device changes more greatly in the Y axis direction, and the saturation current increases greatly in the Y axis direction.The effect of the physical parameters of the. TSV structure on the saturation current of the device is also affected by decreasing the physical parameters in the X axis direction. The smaller TSV radius and the larger thickness of the insulation layer can have a positive effect on the change of the saturation current of the device.In addition, the saturation current of Cu and SiO2 is the largest, followed by the combination of metal Cu and BCB, then the combination of W and BCB, and finally the combination of metal W and SiO2.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386.1

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本文編號：1759909