采用改進型Fibonacci序列DAC設(shè)計技術(shù)研究
發(fā)布時間:2018-04-15 19:00
本文選題:數(shù)模轉(zhuǎn)換器 + 分段式電流舵; 參考:《蘇州大學(xué)》2015年碩士論文
【摘要】:隨著信息技術(shù)的高速發(fā)展,數(shù)字通信系統(tǒng)在信息傳輸領(lǐng)域的比重日益加大,數(shù)模轉(zhuǎn)換器(DAC)作為其中的關(guān)鍵部件之一,其性能的要求越來越高。其中高速、高分辨率和寬帶DAC逐漸成為研究的熱門方向。電流舵DAC因為其結(jié)構(gòu)本征高速特性和良好的驅(qū)動能力,被廣泛運用在高速高精度領(lǐng)域。然而,影響電流舵DAC特性的因素有很多,這給芯片設(shè)計帶來一定的困難。本文針對電流舵DAC設(shè)計中的一些難點,對其關(guān)鍵技術(shù)進行改進和驗證。采用SMIC 0.13μm CMOS工藝,設(shè)計了一種12位100MS/s分段式電流舵DAC。在分析、優(yōu)化和比較四種編碼方式的基礎(chǔ)上,折衷考慮毛刺、面積和功耗,最終確定采用6+6分段結(jié)構(gòu)。高6位為溫度計碼,低6位為改進型Fibonacci序列。整體電路由數(shù)字和模擬部分組成,具有雙通道輸出,在1.2V/3.3V(數(shù)字/模擬)雙電源供電下,滿擺幅輸出電流為20m A,DAC總面積為0.263mm2。模擬部分設(shè)計中,電流鏡采用PMOS的Cascode結(jié)構(gòu)來提高其輸出阻抗,采用差分形式的開關(guān)以保證電流通路始終存在并提高輸出擺幅,在其輸出端接有偽管來減小時鐘饋通效應(yīng)。數(shù)字部分設(shè)計中,由于低6位的改進型Fibonacci序列DAC需要將6位數(shù)字信號轉(zhuǎn)換成7位數(shù)字信號單元,因而需要6-7的譯碼器。經(jīng)過真值表、邏輯表達式以及分組方案的不斷優(yōu)化,將低6位分為3+3,其中最低3位分別表示這7位數(shù)字單元,通過中間3位控制8-1選擇器,最終分得7組不同的譯碼器,輸出的信號交由鎖存器進行同步、去抖以及增強開關(guān)的驅(qū)動能力。對DAC原理圖的設(shè)計和仿真都是基于Cadence Spectre軟件平臺,版圖設(shè)計和驗證則是利用Cadence Virtuoso、Calibre和Matlab軟件。后仿結(jié)果為:INL為±0.3595LSB,DNL為±0.3039LSB,正弦輸入信號為15.625MHz、48.4375MHz時差分輸出的SFDR分別為73.92154d B和73.15604d B,總功耗為78.54m W(數(shù)字部分為10.56m W,模擬部分為67.98m W)。仿真結(jié)果表明,采用改進型Fibonacci序列DAC性能優(yōu)越,可廣泛用于無線通信領(lǐng)域。
[Abstract]:With the rapid development of information technology, the proportion of digital communication system in the field of information transmission is increasing. As one of the key components, the performance of digital to analog converter (DAC) is becoming more and more important.Among them, high-speed, high-resolution and wide-band DAC gradually become the hot research direction.The current steering DAC is widely used in high speed and high precision fields because of its intrinsic high speed characteristic and good driving ability.However, there are many factors that affect the DAC characteristics of the current rudder, which brings some difficulties to the chip design.This paper improves and verifies the key technology of current rudder DAC design.Using SMIC 0.13 渭 m CMOS process, a 12-bit 100MS/s segmented current rudder was designed.Based on the analysis, optimization and comparison of the four coding methods, a compromise of burr, area and power consumption is taken into account, and a 66 segment structure is finally adopted.The high 6 bits are thermometer codes and the low 6 bits are modified Fibonacci sequences.The whole circuit is composed of digital and analog parts and has two output channels. Under the power supply of 1.2V / 3.3V (digital / analog) dual power supply, the total area of 20m ADA DAC with full swing output current is 0.263mm ~ 2.In the analog design, the current mirror adopts the Cascode structure of PMOS to improve the output impedance, uses the differential switch to ensure the current path always exists and increases the output swing, and the pseudo-tube is connected to the output to reduce the clock feed-through effect.In the design of the digital part, the 6-7 decoder is needed because the 6-bit modified Fibonacci sequence DAC needs to convert 6-bit digital signal into 7-bit digital signal unit.Through the continuous optimization of truth table, logical expression and grouping scheme, the low 6 bits are divided into 3 3 bits, in which the lowest 3 bits represent the 7 digit units respectively. Through the intermediate 3 bits control 8 1 selector, 7 different decoders are obtained.The output signal is synchronized by the latch, detrembled and enhanced in the drive capacity of the switch.The design and simulation of DAC schematic are based on Cadence Spectre software platform, and layout design and verification are based on Cadence Virtuoso calibre and Matlab software.The following simulation results show that: INL is 鹵0.3595LSB-DNL 鹵0.3039LSB.The sinusoidal input signal is 15.625MHz, 48.4375MHz, the SFDR is 73.92154dB and 73.15604dB, the total power consumption is 78.54mWW (digital part is 10.56mWW, analog part is 67.98mWN).The simulation results show that the improved Fibonacci sequence DAC has excellent performance and can be widely used in wireless communication field.
【學(xué)位授予單位】:蘇州大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2015
【分類號】:TN792
【參考文獻】
相關(guān)期刊論文 前1條
1 蒲釔霖;石玉;吳斌;葉茂;;一種11位80MS/s分段式電流舵DAC的設(shè)計與驗證[J];微電子學(xué);2014年01期
相關(guān)碩士學(xué)位論文 前1條
1 李儒;16位高速分段電流舵CMOS D/A轉(zhuǎn)換器設(shè)計[D];西安電子科技大學(xué);2011年
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