本文選題：電荷共享 + SRAM單元　； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：隨著集成電路制造工藝的發(fā)展,器件特征尺寸不斷減小,器件間距也隨之減小。當(dāng)輻射環(huán)境中的高能粒子轟擊半導(dǎo)體器件靈敏區(qū)域時(shí),會(huì)在其敏感節(jié)點(diǎn)收集電荷,進(jìn)而引發(fā)單粒子翻轉(zhuǎn)效應(yīng)或單粒子瞬態(tài)脈沖效應(yīng)。當(dāng)特征尺寸進(jìn)入納米級(jí)尺度時(shí),電荷共享效應(yīng)將成為該領(lǐng)域重要的可靠性問(wèn)題之一。電荷共享不僅能導(dǎo)致存儲(chǔ)單元發(fā)生多位翻轉(zhuǎn),還會(huì)使組合邏輯中產(chǎn)生多個(gè)單粒子瞬態(tài)脈沖,使系統(tǒng)的軟錯(cuò)誤率增加,從而加大抗輻射設(shè)計(jì)的難度。目前國(guó)內(nèi)對(duì)電荷共享效應(yīng)的研究主要集中于分立的MOS管之間,且主要考慮90 nm以上的工藝,并沒(méi)有考慮存儲(chǔ)單元和更小特征尺寸時(shí)電荷共享效應(yīng)的影響或作用。因此,有必要從這些方面對(duì)電荷共享效應(yīng)進(jìn)行具體的研究分析,將其對(duì)電路的影響進(jìn)行有針對(duì)性的加固。本文基于TCAD軟件三維器件模型仿真,對(duì)40 nm CMOS工藝器件中的電荷共享效應(yīng)做了深入的分析和研究,使用的SPICE模型為基于IBM 40 nm CMOS工藝模型。本文完成的主要研究工作包括:(1)40 nm工藝器件三維建模。通過(guò)查閱相關(guān)資料,建立了與IBM 40 nm CMOS工藝SPICE模型校準(zhǔn)的晶體管三維器件模型。(2)不同因素對(duì)電荷共享效應(yīng)的影響。研究了40 nm工藝中STI深度、粒子入射角度以及N型深阱的存在對(duì)電荷共享的影響。發(fā)現(xiàn)40 nm工藝中STI在500 nm時(shí)為抑制NMOS間電荷共享收集的有效深度;PMOS間電荷共享隨STI增大呈線性下降;角度入射和N型深阱的引入會(huì)極大的增加NMOS間的電荷共享收集。(3)40 nm工藝中,電荷共享效應(yīng)對(duì)單粒子瞬態(tài)(SET)脈寬和SRAM單元單粒子翻轉(zhuǎn)(SEU)的影響。發(fā)現(xiàn)電荷共享的增加會(huì)抑制SET脈寬,并且在角度入射和三阱工藝中,SRAM單元會(huì)在電荷共享較大時(shí)發(fā)生翻轉(zhuǎn)恢復(fù)。設(shè)計(jì)了新的版圖結(jié)構(gòu),該結(jié)構(gòu)可以充分利用NMOS間電荷共享,將不同NMOS間距時(shí)的翻轉(zhuǎn)恢復(fù)閾值降低20%以上。(4)抑制電荷收集的方法研究。證明了90 nm工藝中常用的“保護(hù)漏”結(jié)構(gòu)在40nm工藝中的不適用性。提出了新的抑制電荷單點(diǎn)收集和共享收集的附加電極結(jié)構(gòu),該結(jié)構(gòu)將單點(diǎn)電荷收集量降低15%以上,使SRAM單元翻轉(zhuǎn)閾值增大0.4 Me V·cm2/mg,并可以有效抑制NMOS間電荷共享和SRAMs發(fā)生MBU。
[Abstract]:With the development of IC manufacturing process, the characteristic size of the device decreases and the device spacing decreases.When the high-energy particles bombarded the sensitive region of semiconductor devices in the radiation environment, they would collect charges at their sensitive nodes, which would lead to the single-particle flip effect or the single-particle transient pulse effect.Charge sharing effect will become one of the important reliability problems in this field when the characteristic size reaches nanometer scale.Charge sharing can not only cause memory cells to flip, but also cause multiple single particle transient pulses in combinational logic, increase the soft error rate of the system, and increase the difficulty of anti-radiation design.At present, the research on the charge sharing effect is mainly focused on the discrete MOS transistor, and mainly considers the process above 90 nm, and does not consider the effect or action of the charge sharing effect when the memory cell and the smaller characteristic size are not taken into account.Therefore, it is necessary to study and analyze the charge-sharing effect from these aspects, and strengthen the effect on the circuit.Based on the 3D device model simulation of TCAD software, the charge-sharing effect in 40nm CMOS process is analyzed and studied in this paper. The SPICE model is based on IBM 40nm CMOS process model.The main research work in this paper includes the 3D modeling of the 40 nm process device.Based on the relevant data, the effect of different factors on the charge-sharing effect is established, which is calibrated with the SPICE model of IBM 40nm CMOS process.The effects of the depth of STI, the incident angle of particles and the existence of N-type deep well on the charge sharing in 40nm process are studied.It is found that the effective depth of STI for suppressing the collection of charge sharing between NMOS at 500nm decreases linearly with the increase of STI, and the incidence of angle and the introduction of N-type deep well will greatly increase the charge-sharing collection among NMOS at 40nm.The effect of charge sharing on the pulse width of single particle transient set and the single particle flip of SRAM unit.It is found that the increase of charge sharing can inhibit the pulse width of SET, and the flip recovery of SET cells occurs when the charge sharing is larger in the angle-incident and three-well processes.A new layout structure is designed, which can make full use of the charge sharing between NMOS to reduce the reverse recovery threshold of different NMOS spacing by more than 20%.It is proved that the "protection leakage" structure commonly used in 90 nm process is not applicable in 40nm process.A new additional electrode structure for suppressing charge collection and sharing collection is proposed. The structure reduces the charge collection by more than 15%, increases the flip threshold of SRAM cell by 0.4 me V cm 2 / mg, and can effectively inhibit the charge sharing between NMOS and the occurrence of SRAMs.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN405

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