本文選題：時鐘管理 + FPGA��； 參考：《深圳大學》2015年碩士論文

【摘要】：自1985年第一塊FPGA(Field-Programmable Gate Array)芯片面世至今只有30年的歷史,但作為一個新興產(chǎn)業(yè),FPGA已經(jīng)取得了輝煌的成就。目前,FPGA產(chǎn)品已從最初的通信設(shè)備擴展到控制、導航、航天、航空等各種軍用、民用領(lǐng)域。作為一種可編程的ASIC(Application Specific Integrated Circuit),FPGA不僅克服了定制電路的諸多不足也解決了前幾代可編程器件門電路數(shù)有限的問題,它已經(jīng)成為數(shù)字系統(tǒng)設(shè)計的基礎(chǔ)之一。時鐘管理模塊(DCM)是FPGA芯片的不可缺少的組成部分,DCM管理整個FPGA系統(tǒng)的時鐘。時鐘偏差和時鐘抖動是電路系統(tǒng)中存在的主要問題,時鐘管理模塊能否正確工作直接影響FPGA的功能和性能,尤其是在高速運行的系統(tǒng)中。目前,系統(tǒng)的時鐘管理方案一般基于鎖相環(huán)或者延時鎖相環(huán)電路。FPGA中時鐘管理主要包括鎖相環(huán)以及時鐘分布網(wǎng)絡(luò)。本文設(shè)計的時鐘管理模塊包括核心單元為全數(shù)字演示鎖相環(huán)(ADDLL)以及與之相結(jié)合的時鐘網(wǎng)絡(luò)兩個部分。按照每個模塊實現(xiàn)的功能可分為鎖定電路(主電路),移相電路(從電路),輸出電路,時鐘網(wǎng)絡(luò)四個模塊。鎖定電路與移相電路都是由鑒相器、控制電路和延時電路等組成。系統(tǒng)工作時,主、從電路分工不同,從電路經(jīng)過延時完成移相,生成相對相位為90°、180°、270°、360°的四個時鐘信號。主電路實現(xiàn)輸入時鐘與從電路生成時鐘其相位最接近信號的同步,實現(xiàn)輸入時鐘與芯片內(nèi)部時鐘的同步。輸出電路除了能輸出同步后的四個相位的時鐘,還能輸出時鐘的多種分頻信號及二倍頻信號。
[Abstract]:It has been only 30 years since the first FPGA(Field-Programmable Gate chip was introduced in 1985, but it has made brilliant achievements as a new industry.At present, FPGA products have been extended from the original communication equipment to control, navigation, aerospace, aviation and other military, civil fields.As a programmable ASIC(Application Specific Integrated circuit, it not only overcomes many shortcomings of custom circuits, but also solves the problem of limited gate number of previous generations of programmable devices. It has become one of the foundations of digital system design.Clock management module (DCM) is an indispensable part of FPGA chip to manage the clock of the whole FPGA system.Clock deviation and clock jitter are the main problems in the circuit system. Whether the clock management module works correctly directly affects the function and performance of FPGA, especially in the high-speed system.At present, the clock management scheme of the system is based on PLL or DPLL circuit. The clock management in FPGA mainly includes PLL and clock distribution network.The clock management module designed in this paper includes two parts: the core unit is an all-digital demonstration phase-locked loop (ADDLL) and the clock network is combined with it.According to the function of each module, it can be divided into four modules: main circuit, phase shift circuit (slave circuit, output circuit, clock network).Lock circuit and phase-shift circuit are composed of phase detector, control circuit and delay circuit.When the system works, the main and slave circuits are divided into different parts, and the phase shift is completed by delay from the circuit to generate four clock signals with a relative phase of 90 擄(180 擄) and 270 擄(360 擄).The main circuit synchronizes the input clock with the phase closest to the signal generated from the circuit, and the input clock synchronizes with the internal clock of the chip.The output circuit can output not only the clock with four phases after synchronization, but also the frequency division signal and the double frequency signal of the clock.
【學位授予單位】：深圳大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791

【參考文獻】

相關(guān)期刊論文 前4條

1 王海力;;淺談國產(chǎn)FPGA芯片的產(chǎn)業(yè)化之路[J];中國電子商情(基礎(chǔ)電子);2013年05期

2 李炎然 ,朱明程;DLL的原理與實現(xiàn)[J];中國集成電路;2005年06期

3 王巍;關(guān)保貞;余敏良;;基于ClockExplorer的時鐘樹插入技術(shù)研究[J];中國集成電路;2012年08期

4 朱曼子;劉伯安;;一種新型混合信號時鐘延時鎖定環(huán)電路設(shè)計[J];微電子學與計算機;2007年03期

，

本文編號：1747155