發(fā)布時間：2018-04-11 02:34

  本文選題：可測試性設計 + 掃描測試��； 參考：《北京工業(yè)大學》2015年碩士論文

【摘要】：隨著集成電路產業(yè)的不斷發(fā)展,芯片的規(guī)模越來越來大,速度越來越快,芯片的測試面臨巨大的挑戰(zhàn)。如何能夠提高芯片的測試質量,降低芯片的測試成本,并且縮短芯片的測試時間,已經成為集成電路領域的研究重點�？蓽y試性設計(Design For Testability,DFT)針對芯片測試中出現的問題,尋求解決方案,其已經成為芯片設計中至關重要的一個環(huán)節(jié)。詳細介紹了可測試性設計的相關原理和概念,并重點分析和討論了芯片中主要包含的故障類型以及目前業(yè)界常用的可測試性設計方法。此外,基于大規(guī)模DSP通訊處理芯片華睿2號中的PCIE IP核,針對該芯片的具體結構和特點,制定出一套完整的可測試設計方案,并完成方案的實施,其中包括掃描測試、存儲器內建自測試以及實速掃描測試,并且完成芯片的測試向量自動生成以及仿真工作。對PCIE的測試覆蓋率、仿真時間、測試時間以及測試功耗進行了深入的研究和討論,并針對PCIE可測試性設計的要求,完成以上幾個方面的優(yōu)化。其中,通過修復寄存器端口不可控以及存儲器周圍陰影邏輯不可測的方法,將掃描測試的測試覆蓋率提升至98.16%;通過掃描壓縮、精簡測試向量以及并行仿真的方法,將掃描測試的仿真時間和測試時間分別降至0.15小時和196.780ms;通過優(yōu)化測試向量無關位以及加入組合邏輯門控技術的方法,將掃描測試功耗降至99.4mW,并且通過加入IEEE P1500結構,將華睿2號芯片頂層的掃描測試峰值功耗較優(yōu)化前降低了86%。除此之外,基于TSMC 45nm工藝,完成了PCIE的物理設計,最終面積為3.866mm×1.945mm。最后,基于對PCIE的研究,總結出一套完整的包含了可測試性設計的芯片設計流程,并重點總結了可測試性設計流程中的各個環(huán)節(jié)。
[Abstract]:With the development of IC industry, the scale and speed of chips are becoming larger and faster.How to improve the quality of the chip test, reduce the cost of the chip test, and shorten the test time of the chip, has become the focus of research in the field of integrated circuits.Testability Design For Testability For (DFT) has become an important part of chip design, which aims at the problems in chip testing and seeks solutions.The related principles and concepts of testability design are introduced in detail, and the main fault types contained in the chip are analyzed and discussed in detail, as well as the commonly used testability design methods in the industry at present.In addition, based on the PCIE IP core in the large-scale DSP communication processing chip Hua Rui 2, according to the specific structure and characteristics of the chip, a complete testability design scheme is developed, and the implementation of the scheme, including scanning test, is completed.Memory built-in test and real speed scan test, and complete the chip test vector automatic generation and simulation work.The test coverage, simulation time, test time and test power consumption of PCIE are studied and discussed in depth, and the above aspects are optimized according to the requirements of PCIE testability design.Among them, by repairing the uncontrollable register port and untestable shadow logic around the memory, the test coverage rate of scanning test is increased to 98.160.The method of scanning compression, reducing test vector and parallel simulation is used.The simulation time and test time of scanning test are reduced to 0.15 hours and 196.780ms respectively, the power consumption of scanning test is reduced to 99.4mW by optimizing test vector independent bit and adding combinational logic gating technology, and the power consumption of scanning test is reduced to 99.4mW by adding IEEE P1500 structure.The peak power consumption of the scan test at the top of Hua Rui 2 chip is 86% lower than that before optimization.In addition, based on TSMC 45nm process, the physical design of PCIE is completed, and the final area is 3.866mm 脳 1.945mm.Finally, based on the research of PCIE, a complete set of chip design flow including testability design is summarized, and each link of testability design flow is emphatically summarized.
【學位授予單位】：北京工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN407

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相關期刊論文 前1條

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本文編號：1734073