本文選題：傳輸線　切入點(diǎn)：信號(hào)完整性　出處：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著集成電路各項(xiàng)技術(shù)和工藝的飛速發(fā)展,片上高速傳輸技術(shù)將面臨更高的要求和更大的挑戰(zhàn)。這是因?yàn)閿?shù)據(jù)傳輸速率的提高會(huì)導(dǎo)致串?dāng)_、損耗和反射等一系列信號(hào)完整性問(wèn)題,又由于線間耦合和對(duì)地耦合帶來(lái)的影響不斷加大,長(zhǎng)互連線上出現(xiàn)了明顯的傳輸線效應(yīng),傳統(tǒng)的RC互連已經(jīng)不能很好地表征信號(hào)高速傳輸時(shí)的各項(xiàng)特性。為了解決上述問(wèn)題,使用傳輸線模型來(lái)代替RC互連模型。同時(shí),高性能的片上收發(fā)器可以進(jìn)一步提高工作頻率,降低互連功耗,在降低信號(hào)衰減和抑制碼間干擾方面也具有明顯的作用。因此,針對(duì)傳輸線模型的高速收發(fā)器研究就變得十分重要。本文首先介紹了片上高速傳輸?shù)难芯勘尘昂鸵饬x,然后從傳輸線模型出發(fā),研究高速傳輸時(shí)會(huì)遇到的信號(hào)完整性問(wèn)題,分析了反射、串?dāng)_和損耗等非理想效應(yīng)的產(chǎn)生原因,給出抑制策略。并針對(duì)片上差分傳輸線,對(duì)互連寄生參數(shù)進(jìn)行了提取,得到寄生電阻、電容和電感的表達(dá)式。其次,為了解決長(zhǎng)距離傳輸過(guò)程中的信道損耗和碼間干擾等問(wèn)題,本文以收發(fā)器的預(yù)加重技術(shù)和時(shí)域均衡技術(shù)為基礎(chǔ),研究了一種可用于片上高速信號(hào)傳輸?shù)腃ML收發(fā)器,并完成版圖的繪制和仿真驗(yàn)證。仿真結(jié)果表明,該收發(fā)器能夠在130nm CMOS混合信號(hào)電路工藝下,實(shí)現(xiàn)5Gbps的高速信號(hào)在10mm長(zhǎng)差分傳輸線上的高性能傳輸。最后為了驗(yàn)證收發(fā)器的實(shí)際功能,基于不同的傳輸線結(jié)構(gòu),設(shè)計(jì)出相應(yīng)的測(cè)試實(shí)驗(yàn)方案。
[Abstract]:With the rapid development of integrated circuit technology and technology, high-speed transmission technology on-chip will face higher requirements and greater challenges.This is because the increase of data transmission rate will lead to a series of signal integrity problems, such as crosstalk, loss and reflection.Traditional RC interconnection can not well characterize the characteristics of high-speed signal transmission.In order to solve the above problem, the transmission line model is used to replace the RC interconnection model.At the same time, the high performance on-chip transceiver can further improve the working frequency, reduce the power consumption of interconnect, and play a significant role in reducing the signal attenuation and inter-symbol interference (ISI).Therefore, the research of high-speed transceiver for transmission line model becomes very important.This paper first introduces the research background and significance of high speed transmission on a chip, then from the transmission line model, studies the signal integrity problems encountered in high speed transmission, and analyzes the causes of non-ideal effects such as reflection, crosstalk and loss.The inhibition strategy is given.The parasitic parameters of interconnect are extracted for the differential transmission line on chip, and the expressions of parasitic resistance, capacitance and inductance are obtained.Secondly, in order to solve the problems of channel loss and inter-symbol interference during long distance transmission, a CML transceiver which can be used for high speed signal transmission on chip is studied based on transceiver preweighting technique and time domain equalization technique.And complete the layout of the drawing and simulation verification.The simulation results show that the transceiver can realize the high performance transmission of the 5Gbps signal on the 10mm long differential transmission line under the 130nm CMOS mixed signal circuit technology.Finally, in order to verify the actual function of transceiver, the corresponding test scheme is designed based on different transmission line structure.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47

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本文編號(hào)：1729652