發(fā)布時(shí)間：2018-04-04 19:15

  本文選題：驗(yàn)證技術(shù)　切入點(diǎn)：功能覆蓋率　出處：《浙江大學(xué)》2015年碩士論文

【摘要】：近年來(lái),集成電路產(chǎn)業(yè)發(fā)生了翻天覆地的變化。隨著制造工藝進(jìn)入納米階段,芯片的速度和集成度不斷上升,由此引發(fā)的芯片功能驗(yàn)證問(wèn)題日益顯著。芯片的驗(yàn)證技術(shù)影響著芯片的性能、成本和設(shè)計(jì)周期,在一定程度上決定了芯片在市場(chǎng)中的生存能力,因此驗(yàn)證技術(shù)的提高已成為IC設(shè)計(jì)者重點(diǎn)關(guān)注的熱點(diǎn)問(wèn)題之一。 本文從芯片驗(yàn)證方法的發(fā)展歷程出發(fā),探討目前功能驗(yàn)證技術(shù)的分類及各自優(yōu)缺點(diǎn)。形式驗(yàn)證主要采用靜態(tài)形式驗(yàn)證方法,適合小規(guī)模組合電路測(cè)試；FPGA驗(yàn)證雖能進(jìn)行軟硬結(jié)合仿真,但信號(hào)可視性較差；仿真性功能驗(yàn)證由于其自身動(dòng)態(tài)驗(yàn)證的特點(diǎn),已成為IC驗(yàn)證的主流方法之一。其中,基于功能覆蓋率驅(qū)動(dòng)的驗(yàn)證方式能提高仿真性功能驗(yàn)證的完備性和可靠性,但提高效率還得取決于隨機(jī)向量的生成。針對(duì)此問(wèn)題,本文提出一種基于遺傳算法的測(cè)試激勵(lì)生成技術(shù),對(duì)基于DMX512協(xié)議的LED解碼芯片進(jìn)行仿真性功能驗(yàn)證,加速功能覆蓋率收斂速度,有效提高驗(yàn)證效率。 本文具體分析研究,主要包括以下幾方面： 第一,對(duì)基于DMX512協(xié)議的LED解碼芯片進(jìn)行設(shè)計(jì)分析,特別是對(duì)驗(yàn)證對(duì)象——DMX512解碼模塊的內(nèi)部架構(gòu)、數(shù)據(jù)幀、時(shí)序等特點(diǎn)進(jìn)行詳細(xì)研究,通過(guò)分析驗(yàn)證對(duì)象特點(diǎn)提取關(guān)鍵信息,制定相應(yīng)的驗(yàn)證計(jì)劃。 第二,簡(jiǎn)要介紹遺傳算法在功能覆蓋率收斂上的應(yīng)用,詳細(xì)分析遺傳算法中適應(yīng)度函數(shù)和三大遺傳算子的選取方法,利用概率分布函數(shù)分析各遺傳算子在本文應(yīng)用中的優(yōu)越性,得到基于比例選擇算子、均勻交叉算子和二元變異算子的優(yōu)秀遺傳算法。 第三,根據(jù)LED解碼模塊的工作特點(diǎn),搭建基于VMM形式的驗(yàn)證平臺(tái),利用System Verilog(SV)高級(jí)驗(yàn)證語(yǔ)言實(shí)現(xiàn)遺傳算法并將其嵌入于驗(yàn)證平臺(tái)中。 第四,利用VMM形式的驗(yàn)證平臺(tái),對(duì)DMX512解碼模塊分別進(jìn)行全隨機(jī)向量測(cè)試和基于遺傳算法的驗(yàn)證向量測(cè)試并分析在不同激勵(lì)下,芯片功能覆蓋率的收斂速度。最后說(shuō)明基于遺傳算法的測(cè)試向量生成技術(shù)能夠加速功能覆蓋率收斂速度,提高驗(yàn)證效率。
[Abstract]:In recent years, the integrated circuit industry has undergone earth-shaking changes.As the manufacturing process enters the nanometer stage, the speed and integration of the chip are rising, and the problem of chip function verification is becoming more and more obvious.Chip verification technology affects the chip performance, cost and design cycle, to a certain extent, determines the viability of the chip in the market, so the improvement of verification technology has become one of the hot issues that IC designers focus on.Starting from the development of chip verification methods, this paper discusses the classification of current functional verification techniques and their respective advantages and disadvantages.The formal verification mainly adopts the static formal verification method, which is suitable for the FPGA verification of small-scale combinational circuit testing, although it can carry out the soft and hard combination simulation, but the signal visibility is poor, the simulation function verification is due to its own characteristics of dynamic verification.It has become one of the main methods of IC verification.Among them, the verification method based on function coverage driving can improve the completeness and reliability of simulation function verification, but improving efficiency depends on the generation of random vectors.To solve this problem, this paper presents a test excitation generation technique based on genetic algorithm, which simulates the performance of LED decoding chip based on DMX512 protocol, accelerates the convergent speed of function coverage, and effectively improves the efficiency of verification.In this paper, the specific analysis and research, mainly including the following aspects:First, the LED decoding chip based on DMX512 protocol is designed and analyzed, especially the internal structure, data frame, timing and other characteristics of the verification object-DMX512 decoding module are studied in detail, and the key information is extracted by analyzing the characteristics of the verification object.Make corresponding verification plan.Secondly, the application of genetic algorithm in the convergence of function coverage is briefly introduced. The selection methods of fitness function and three genetic operators in genetic algorithm are analyzed in detail, and the superiority of each genetic operator in this paper is analyzed by using probability distribution function.An excellent genetic algorithm based on proportional selection operator, uniform crossover operator and binary mutation operator is obtained.Thirdly, according to the working characteristics of LED decoding module, a verification platform based on VMM is built, and the genetic algorithm is implemented by System Verilog SVS and embedded in the verification platform.Fourthly, using the VMM verification platform, the full random vector test and the verification vector test based on genetic algorithm are carried out for the DMX512 decoding module, and the convergence rate of chip function coverage is analyzed under different excitations.Finally, it is shown that the test vector generation based on genetic algorithm can accelerate the convergence rate of function coverage and improve the efficiency of verification.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN312.8

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本文編號(hào)：1711311