本文選題：資源約束　切入點(diǎn)：批處理機(jī)　出處：《西南交通大學(xué)》2015年碩士論文

【摘要】：隨著信息產(chǎn)業(yè)的蓬勃發(fā)展,半導(dǎo)體制造業(yè)已經(jīng)成為國(guó)民經(jīng)濟(jì)的前驅(qū)發(fā)展產(chǎn)業(yè)。成本高、工序多、流程復(fù)雜為其特有屬性。因此,如何提高設(shè)備利用率,對(duì)客戶需求快速做出響應(yīng),并對(duì)有限的資源進(jìn)行合理的分配利用成為了半導(dǎo)體制造業(yè)調(diào)度的目標(biāo)。半導(dǎo)體集成電路生產(chǎn)線有前端工藝和后端工藝之分。前端工藝經(jīng)過(guò)大量學(xué)者的研究,針對(duì)每個(gè)問(wèn)題大都得到很好的優(yōu)化方案,這就使得后端工藝流程中的問(wèn)題凸顯出來(lái)。對(duì)后端測(cè)試階段集成電路芯片的優(yōu)化調(diào)度可以有效地提高整個(gè)工藝流程的生產(chǎn)效益。后端測(cè)試階段的調(diào)度問(wèn)題大多數(shù)為NP-hard.再加上設(shè)備產(chǎn)能約束,以及工件加工過(guò)程中所需要的機(jī)器手、托盤(pán)等附屬資源的約束,這就使得問(wèn)題進(jìn)一步復(fù)雜化。本文對(duì)多種資源約束下的半導(dǎo)體最終測(cè)試階段的批處理機(jī)問(wèn)題進(jìn)行優(yōu)化。我們首先針對(duì)單批處理機(jī)問(wèn)題進(jìn)行分析研究,建立問(wèn)題的數(shù)學(xué)模型,并設(shè)計(jì)變鄰域搜索算法(variable neighborhood search algorithm, VNS)、基于隨機(jī)鍵的遺傳算法(random key genetic algorithm, RKGA)以及基于批的插入算法(batch of insertion algorithm, BIA),最后通過(guò)數(shù)據(jù)仿真實(shí)驗(yàn),將其與先前文獻(xiàn)中的oven first batch first fit (OFBFF)啟發(fā)式算法和一般遺傳算法進(jìn)行對(duì)比并對(duì)各算法的優(yōu)劣性進(jìn)行分析比較。之后本文將單批處理機(jī)調(diào)度問(wèn)題擴(kuò)展為同型號(hào)平行(identical parallel)批處理機(jī)調(diào)度問(wèn)題,針對(duì)該問(wèn)題我們根據(jù)多批處理機(jī)芯片生產(chǎn)流程的不同提出兩種解決方案,其中每種解決方案都把問(wèn)題分解為四個(gè)階段,并分別設(shè)計(jì)出基于先組批再分配的批插入算法(first batching then machine- batch of insertion algorithm, FBTM-BIA)和基于先分配后組批的批插入算法(first machine then batching-batch of insertion algorithm, FMTB-BIA),通過(guò)仿真實(shí)驗(yàn)分析兩種算法表現(xiàn)。
[Abstract]:With the rapid development of information industry, semiconductor manufacturing industry has become the leading industry of national economy.High cost, many processes, complex process is its unique attribute.Therefore, how to improve the utilization rate of equipment, to respond to customer demand quickly, and to allocate and utilize the limited resources rationally has become the target of semiconductor manufacturing scheduling.Semiconductor integrated circuit production line has front-end process and back-end process.After a lot of scholars' research, the front-end process gets a good optimization scheme for each problem, which makes the problems in the back-end process prominent.The optimal scheduling of IC chips in the back-end test stage can effectively improve the production efficiency of the whole process.Most scheduling problems in the back-end test phase are NP-hard.In addition, the constraints of equipment capacity, and the constraints of machine hands, pallet and other ancillary resources needed in the process of workpiece processing further complicate the problem.In this paper, the batch problem in the final testing phase of semiconductors with multiple resource constraints is optimized.First of all, we analyze and study the problem of single batch processor, and set up the mathematical model of the problem.Then this paper extends the single batch processor scheduling problem to the same type parallel parallel parallel batch processor scheduling problem. In view of this problem, we propose two solutions according to the different production processes of multi-batch processing machine chips.Each of these solutions breaks down the problem into four phases,The first batching then machine- batch of insertion algorithm (FBTM-BIA) and the first machine then batching-batch of insertion algorithm (FMTB-BIAA) are designed, respectively. The performance of the two algorithms is analyzed by simulation experiments.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN407

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本文編號(hào)：1702312