本文選題：結(jié)型場(chǎng)板　切入點(diǎn)：LDMOS　出處：《電子科技大學(xué)》2015年碩士論文

【摘要】：為實(shí)現(xiàn)橫向功率器件的高耐壓和低導(dǎo)通電阻特性,本文提出了一種新型結(jié)型場(chǎng)板技術(shù)。結(jié)型場(chǎng)板技術(shù)不僅保持了傳統(tǒng)阻性場(chǎng)板在調(diào)制器件表面電場(chǎng)方面的優(yōu)勢(shì),而且解決了阻性場(chǎng)板泄漏電流大的問(wèn)題,對(duì)器件靜態(tài)電學(xué)性能的提高具有非常大的作用。本文將結(jié)型場(chǎng)板技術(shù)應(yīng)用在LDMOS上,提出了兩種新的LDMOS器件。1.一種具有結(jié)型場(chǎng)板的REBULF(REduced BULk Field)LDMOS。本文將新型結(jié)型場(chǎng)板技術(shù)和REBULF技術(shù)應(yīng)用于具有薄外延導(dǎo)電層的高壓LDMOS上,提出了JFP-REBULF(Junction Field Plate-Partial N-buried layer)LDMOS結(jié)構(gòu)。結(jié)型場(chǎng)板不僅可以調(diào)節(jié)功率器件的表面電場(chǎng),還能與漂移區(qū)形成MIS結(jié)構(gòu),輔助耗盡漂移區(qū),增加漂移區(qū)摻雜濃度。REBULF技術(shù)在襯底內(nèi)引入了一個(gè)縱向的PN結(jié),可擴(kuò)展襯底縱向耗盡深度,提高器件的縱向耐壓。在兩種技術(shù)的共同作用下,JFPREBULF LDMOS在耐壓達(dá)到740V的同時(shí),比導(dǎo)通電阻可以低至67.3 mΩ·cm2。相對(duì)于傳統(tǒng)同尺寸的具有一階金屬場(chǎng)板的LDMOS來(lái)說(shuō),耐壓提高了67.4%,比導(dǎo)通電阻降低了45.7%。本文還根據(jù)與我們合作的生產(chǎn)線的工藝條件設(shè)計(jì)了JFPREBULF LDMOS的工藝流程,并制作了版圖。2.一種具有結(jié)型場(chǎng)板的LDMOS�？紤]到有些應(yīng)用情況下可以使用電阻率高的硅襯底,縱向耐壓不再是薄外延層功率器件的“短板”,本文提出了JFP LDMOS。結(jié)型場(chǎng)板在提高器件的耐壓的同時(shí)還大大地降低了器件的導(dǎo)通電阻。器件的縱向耐壓則基本上都由具有低摻雜濃度的襯底承擔(dān)。與JFP-REBULF LDMOS相比,JFP LDMOS無(wú)需制作部分N埋層結(jié)構(gòu),簡(jiǎn)化了制造工藝并降低了成本。經(jīng)過(guò)仿真優(yōu)化設(shè)計(jì)器件參數(shù)獲得JFP LDMOS的耐壓為679V,比導(dǎo)通電阻為62.4mΩ?cm2,相對(duì)于傳統(tǒng)的具有一階金屬場(chǎng)板的LDMOS,耐壓提高了26.7%,比導(dǎo)通電阻降低了66.4%。最后,本文給出了這種器件的工藝步驟。
[Abstract]:In order to realize the characteristics of high voltage and low on-resistance of transverse power devices, a new type of junction field plate technology is proposed in this paper, which not only maintains the advantage of the traditional resistive field plate in the surface electric field of modulating devices, but also keeps the advantages of the traditional resistive field plate in the surface electric field of modulating devices. Moreover, the problem of large leakage current of resistive field plate is solved, which plays an important role in improving the static electrical performance of the device. In this paper, the junction field plate technology is applied to LDMOS. Two new LDMOS devices are proposed. 1. A new type of REBULF(REduced BULk FieldMoss with junction field plate is proposed. In this paper, a novel junction field plate technique and REBULF technique are applied to high voltage LDMOS with thin epitaxial conductive layer. The JFP-REBULF(Junction Field Plate-Partial N-buried layer)LDMOS structure is proposed. The junction field plate can not only adjust the surface electric field of the power device, but also form MIS structure with the drift region to assist the depletion drift region. A longitudinal PN junction is introduced into the substrate by increasing the drift region doping concentration. It can extend the longitudinal depletion depth of the substrate and improve the longitudinal voltage resistance of the device. The JFPREBULF LDMOS can withstand a voltage of 740V at the same time under the combined action of the two techniques. The specific on-resistance can be as low as 67.3 m 惟 cm2.Compared with the conventional LDMOS with the same size of the first order metal field plate, The voltage resistance is increased by 67.4%, and the on-resistance is reduced by 45.7%. The process of JFPREBULF LDMOS is also designed according to the technological conditions of the production line that we are cooperating with. A kind of LDMOS with junction field plate is fabricated. Considering that silicon substrate with high resistivity can be used in some applications, The longitudinal voltage resistance is no longer the "short board" of the thin epitaxial layer power device. In this paper, it is proposed that the junction field board not only improves the device's voltage resistance, but also greatly reduces the on-resistance of the device. Compared with JFP-REBULF LDMOS, the substrate with low doping concentration does not need to fabricate part of the N-buried structure. The fabrication process is simplified and the cost is reduced. By optimizing the design parameters of the device, the voltage of JFP LDMOS is 679V and the specific on-resistance is 62.4m 惟? Cm _ 2, compared with the conventional LDMOS with first-order metal field plates, increases the voltage by 26.7 and reduces the on-resistance by 66.4. finally, the process steps of this device are given in this paper.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

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