本文選題：CLB　切入點(diǎn)：FPGA　出處：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：FPGA (Field Programable Gate Array)即現(xiàn)場可編程門陣列,是在PAL(Programable Array Logic)、GAL(Gate Array Logic)、CPLD(Complex Programable Logic Device)等可編程器件的基礎(chǔ)上進(jìn)一步發(fā)展的產(chǎn)物。作為專用集成電路(ASIC)領(lǐng)域中的一種半定制電路,既解決了定制電路的不足,又克服了原有可編程器件門電路數(shù)有限的缺點(diǎn)。相比于國際FPGA公司多年的發(fā)展積累,國內(nèi)FPGA技術(shù)的發(fā)展處于起步階段,西安智多晶微電子抓住國產(chǎn)FPGA設(shè)計(jì)的迫切需求,依據(jù)客戶定制的要求,設(shè)計(jì)了IST系列FPGA。論文基于IST項(xiàng)目中的FPGA可配置電路CLB(Configure Logic Block)的設(shè)計(jì)與優(yōu)化,深入研究了FPGA器件邏輯配置模塊的核心結(jié)構(gòu)和原理,設(shè)計(jì)和優(yōu)化CLB電路結(jié)構(gòu)和性能,采用55nnm標(biāo)準(zhǔn)CMOS工藝,利用全定制設(shè)計(jì)方法設(shè)計(jì)電路,采用標(biāo)準(zhǔn)的全定制流程,利用VCS作為功能驗(yàn)證工具,利用Hspice做性能分析和優(yōu)化,在工藝和工具上都有先進(jìn)性,在設(shè)計(jì)原理上具有獨(dú)創(chuàng)性。主要內(nèi)容有如下：1.利用自上而下的設(shè)計(jì)方法,完成了CLB的核心單元PFU從頂層的結(jié)構(gòu)設(shè)計(jì)到底層的模塊實(shí)現(xiàn)。詳細(xì)闡述了PFU的設(shè)計(jì)原理和思路,包括PFU的頂層設(shè)計(jì)以及模塊劃分,PFU核心模塊Slice的頂層設(shè)計(jì)和Slice三大工作模式(Ripple mode, Logic mode, RAM mode)的功能定義,以及Slice在每種工作模式下的每個功能點(diǎn)的設(shè)計(jì)方案,完成了Slice功能要求的加法器、減法器、上行計(jì)數(shù)器、下行計(jì)數(shù)器,比較器、乘法器的設(shè)計(jì),完成了規(guī)格要求的RAM模式電路的設(shè)計(jì),實(shí)現(xiàn)了單雙口RAM、信號連接和RAM的容量擴(kuò)張。2.針對CLB的特點(diǎn),搭建了具有高效率和符合CLB特點(diǎn)的驗(yàn)證平臺,利用VCS工具,驗(yàn)證了CLB的各種模式以及其對應(yīng)的功能的正確性。利用自動比對的標(biāo)準(zhǔn)位和波形的詳細(xì)分析,完備而又直觀的驗(yàn)證了CLB的功能,證明設(shè)計(jì)結(jié)果正確且符合要求。3.基于FPGA芯片對應(yīng)的編程軟件設(shè)計(jì)的要求和目標(biāo)規(guī)格(Target spec)中的性能要求,對CLB的設(shè)計(jì)做了版圖后仿真,在添加了寄生參數(shù)的前提下,分析各功能電路的負(fù)載并正確合理加入負(fù)載,同時利用Hspice的高精度器件時序模型,對目標(biāo)規(guī)格要求的各功能的路徑延時做了仿真,得到具體延時數(shù)據(jù),并不斷修改設(shè)計(jì)和器件尺寸,使仿真的延時達(dá)到規(guī)格要求,同時分析關(guān)鍵信號的波形,保證信號的完整性,達(dá)到了項(xiàng)目的性能指標(biāo)要求。
[Abstract]:FPGA field Programable Gate array is the product of further development on the basis of PAL(Programable Array logic gate Array logic device and so on. As a semi-custom circuit in the field of ASICs, it solves the deficiency of custom circuit. Compared with the development and accumulation of international FPGA company for many years, the development of domestic FPGA technology is in its infancy, and Xi'an Zhi polycrystalline microelectronics seize the urgent need of domestic FPGA design. According to the requirements of customer customization, the IST series FPGA is designed. Based on the design and optimization of FPGA configurable circuit CLB(Configure Logic Block in the IST project, the core structure and principle of FPGA logic configuration module are deeply studied. To design and optimize the structure and performance of CLB circuit, adopt 55nnm standard CMOS process, design circuit with full custom design method, adopt standard full customization flow, use VCS as function verification tool, use Hspice to do performance analysis and optimization. Advanced in technology and tools, originality in design principle. The main contents are as follows: 1.Using top-down design method, In this paper, the core unit of CLB, PFU, is designed from the top structure to the bottom module. The design principle and thought of PFU are described in detail. Including the top-level design of PFU and the top-level design of Slice, the core module of Slice, and the definition of the functions of three working modes of Slice: Ripple mod, Logic mode, RAM mode, and the design scheme of each function point of Slice in each working mode. The design of the adder, subtracter, uplink counter, downlink counter, comparator and multiplier for Slice function requirement is completed. The design of RAM mode circuit with specifications is completed. The single and double port RAM, signal connection and capacity expansion of RAM are realized. According to the characteristics of CLB, a verification platform with high efficiency and accord with the characteristics of CLB is built, and the VCS tool is used. The correctness of various modes and corresponding functions of CLB is verified. The function of CLB is verified completely and intuitively by the detailed analysis of standard bits and waveforms of automatic alignment. It is proved that the design results are correct and accord with the requirements .3.Based on the requirements of programming software design corresponding to FPGA chip and the performance requirements in target specification, the post-layout simulation of the design of CLB is done, and the parasitic parameters are added to the design. The load of each functional circuit is analyzed and the load is added correctly and reasonably. At the same time, the path delay of each function required by the target specification is simulated by using the high-precision device timing model of Hspice, and the specific delay data are obtained. The design and the device size are modified constantly to make the simulation delay meet the specification requirements. At the same time, the waveform of the key signal is analyzed to ensure the integrity of the signal, and the performance requirements of the project are met.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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本文編號：1656202