本文選題：功控單軌電流模電路　切入點(diǎn)：功控休眠技術(shù)　出處：《寧波大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著集成電路芯片在電子產(chǎn)品上的運(yùn)用越來(lái)越廣泛,芯片的功耗問(wèn)題也得到極大的關(guān)注,提高工作速度,減小芯片功耗也成了目前許多研究學(xué)者的重要目標(biāo)。目前已有的減小功耗技術(shù)有許多,比如,雙閾值技術(shù),溝道長(zhǎng)度偏置技術(shù),輸入矢量控制以及功控休眠技術(shù)。其中,功控休眠技術(shù)能夠有效的減小空閑狀態(tài)下的功耗,從而能達(dá)到減小總功耗的目的。因此,要想進(jìn)一步實(shí)現(xiàn)高速、低功耗設(shè)計(jì),將功控休眠技術(shù)運(yùn)用到單軌電流模電路中,實(shí)現(xiàn)高速電路的同時(shí)降低空閑狀態(tài)下的功耗是一項(xiàng)非常重要的目標(biāo)。本學(xué)位論文研究了低功耗設(shè)計(jì)技術(shù)以及傳統(tǒng)CMOS電路的功耗組成。將功控休眠技術(shù)很好的運(yùn)用到單軌電流模邏輯電路中,并從電路建模分析、功控技術(shù)設(shè)計(jì)、近閾值電路設(shè)計(jì)等多方面對(duì)它進(jìn)行功耗減小的研究。本文可分為以下幾個(gè)部分:1、介紹低功耗設(shè)計(jì)技術(shù)的研究背景,分析功控單軌電流模設(shè)計(jì)技術(shù)研究的重要性。2、介紹電流模電路的工作原理以及雙軌電流模電路的電路結(jié)構(gòu),并對(duì)單軌電流模電路設(shè)計(jì)需要注意的性能參數(shù)特點(diǎn)進(jìn)行分析,這為后面將新的技術(shù)運(yùn)用到單軌電流模上做準(zhǔn)備。3、分析傳統(tǒng)靜態(tài)CMOS功控休眠技術(shù)的工作原理以及其性能參數(shù),根據(jù)功控休眠技術(shù)的特點(diǎn),將這種技術(shù)用于單軌電流模電路中,對(duì)功控單軌電流模電路進(jìn)行建模分析,研究功控單軌電流模電路在工作狀態(tài)和休眠狀態(tài)時(shí)的功耗來(lái)源,以及分析功控休眠晶體管的尺寸的改變會(huì)產(chǎn)生的影響。設(shè)計(jì)新型的功控單軌電流模觸發(fā)器,從結(jié)構(gòu)上優(yōu)化功控單軌電流模電路的功耗。將設(shè)計(jì)的功控單軌電流模電路與傳統(tǒng)靜態(tài)CMOS電路以及非功控的電流模電路進(jìn)行對(duì)比,結(jié)果顯示功控單軌電流模電路在漏功耗減小方面有顯著的優(yōu)勢(shì)。4、結(jié)合功控單軌電流模電路的工作特性,采用近閾值設(shè)計(jì)技術(shù)進(jìn)一步優(yōu)化電路的性能。在近閾值條件下,分析了功控單軌電流模電路能正常工作的最小工作電壓,并比較了功控單軌電流模電路、電流模電路以及傳統(tǒng)靜態(tài)CMOS電路在不同工作電壓時(shí)候的性能參數(shù)。研究結(jié)果顯示將近閾值設(shè)計(jì)技術(shù)運(yùn)用到功控單軌電流模電路中能夠有效的減小功耗和延時(shí)。
[Abstract]:With the application of IC chips in electronic products more and more widely, the problem of chip power consumption has been paid great attention to, and the speed of work has been improved. Reducing chip power consumption has also become an important goal of many researchers. There are many existing power reduction technologies, such as dual-threshold technology, channel length bias technology, input vector control and power control sleep technology. Power control sleep technology can effectively reduce the power consumption in idle state, so that the total power consumption can be reduced. Therefore, in order to further realize the design of high speed and low power consumption, power control sleep technology is applied to monorail current mode circuit. It is a very important goal to realize high speed circuits and reduce the power consumption in idle state. This dissertation studies the low power design technology and the power composition of traditional CMOS circuits. To a monorail current-mode logic circuit, And from the circuit modeling analysis, power control technology design, near threshold circuit design and other aspects of its power consumption reduction. This paper can be divided into the following parts: 1, introduce the research background of low-power design technology, This paper analyzes the importance of the research on power control monorail current mode design, introduces the working principle of the current mode circuit and the circuit structure of the dual track current mode circuit, and analyzes the characteristics of the performance parameters which should be paid attention to in the design of the monorail current mode circuit. This is the preparation for the application of the new technology to the monorail current mode. 3. The working principle and performance parameters of the traditional static CMOS power control dormancy technology are analyzed. According to the characteristics of the power control dormancy technology, this technology is used in the monorail current mode circuit. Modeling and analysis of power-controlled monorail current-mode circuit is carried out to study the power consumption source of power-controlled monorail current-mode circuit in working and dormant state. And analyze the influence of the size change of power control dormant transistor. Design a new type of power-controlled monorail current-mode flip-flop, The power consumption of power-controlled monorail current-mode circuit is optimized from structure. The power control monorail current-mode circuit is compared with traditional static CMOS circuit and non-power-controlled current-mode circuit. The results show that power control monorail current-mode circuit has significant advantages in reducing leakage power consumption. Combined with the working characteristics of power-controlled monorail current-mode circuit, the near-threshold design technique is used to further optimize the performance of the circuit. The minimum operating voltage of power control monorail current mode circuit is analyzed, and the power control monorail current mode circuit is compared. The performance parameters of the current mode circuit and the traditional static CMOS circuit under different operating voltages. The results show that the near-threshold design technology can effectively reduce power consumption and delay in power-controlled monorail current-mode circuits.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402

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本文編號(hào)：1650845