本文選題：模擬電路　切入點：折疊共源共柵放大器　出處：《哈爾濱工業(yè)大學》2015年碩士論文　論文類型：學位論文

【摘要】：隨著各國航空航天事業(yè)的不斷發(fā)展,越來越多的電子系統(tǒng)運用于航天設備中。而電子元器件一旦暴露在溫度多變、輻射強度極高的太空環(huán)境中,其可靠性將勢必受到嚴重影響。集成電路的工藝尺寸不斷縮減,時鐘頻率,各類寄生效應的影響不斷增加,這些因素促使國內外對輻射效應的研究逐漸聚焦在模擬電路的單粒子瞬態(tài)效應(SET)上,SET效應成為所有單粒子效應(SEE)中對軟錯誤率貢獻最大的輻射效應。在模擬電路中,單個高能粒子撞擊器件敏感節(jié)點時,會在器件內部產生過量載流子從而引起在電路總輸出電壓的瞬態(tài)波動。基于運算放大器在模擬以及混合電路設計中的重要地位以及SET效應研究的必要性,本文選定折疊共源共柵放大器作為研究對象,主要對SET效應的作用機理及敏感性進行分析并分別針對放大器電路的各組成部分采用兩種電荷抵消加固方法并進行了相應的分析和驗證。首先在對模擬電路中的SET效應作用機理及影響進行詳細了解的基礎上,采用SMIC 0.18μm工藝,設計出符合一定性能指標的折疊共源共柵放大器電路;然后運用工藝計算機輔助設計系統(tǒng)(TCAD)建模工具選取出放大器各部分的SET敏感節(jié)點。在此過程中首先要對電路中的各MOS器件進行多維建模并運用建立好的模型對整體電路進行混合仿真研究,之后采用臨界電荷值、總輸出Vout發(fā)生翻轉的瞬變脈寬以及波谷值等參數對放大器敏感節(jié)點進行選取;最后,對電路各部分敏感節(jié)點進行抗SET效應加固設計,運用多敏感節(jié)點自電荷抵消技術(M-SNACC)以及差分電荷抵消(DCC)布局技術分別對運算放大器進行電路級和版圖級的加固設計。給出整體加固版圖及相應仿真結果并對加固前后放大器各性能指標的變化進行研究分析。
[Abstract]:With the continuous development of aerospace industry in various countries, more and more electronic systems are used in spaceflight equipment, and once electronic components are exposed to variable temperature and extremely high radiation intensity in space environment, Its reliability is bound to be seriously affected. The process size of integrated circuits is continuously reduced, and the effects of clock frequency and parasitic effects are increasing. These factors have led to the study of radiation effects at home and abroad, focusing gradually on the single particle transient effect (set) of analog circuits, which has become the largest contribution to soft error rate of all single particle effects (SEE). In analog circuits, When a single high-energy particle impacts the sensitive node of the device, It can cause transient fluctuations in the total output voltage of the circuit due to excessive carriers in the device. Based on the importance of operational amplifiers in analog and hybrid circuit design and the necessity of studying the SET effect, In this paper, the folded common-gate amplifier is chosen as the research object. The mechanism and sensitivity of SET effect are analyzed, and two kinds of charge canceling reinforcement methods are adopted for each component of amplifier circuit respectively. On the basis of detailed understanding of the mechanism and effect of SET effect, By using SMIC 0.18 渭 m process, a folded common-gate amplifier circuit with certain performance index is designed. Then the SET sensitive nodes of each part of the amplifier are selected by using the process computer aided Design (CAD) modeling tool. In this process, the multi-dimensional modeling of each MOS device in the circuit is carried out and the integrated model is applied to the whole circuit. The hybrid simulation of bulk circuit is carried out. Then the critical charge value, transient pulse width and trough value of total output Vout are used to select the sensitive node of amplifier. Finally, the anti-#en1# effect reinforcement design of each sensitive node of the circuit is carried out. Using multi-sensitive node self-charge canceling technique (M-SNACC) and differential charge canceller (DCC-DCC), the circuit level and layout level of the operational amplifier are designed respectively. The overall reinforcement layout and corresponding simulation results are given and the reinforcement results are given. The changes of each performance index of the amplifier before and after are studied and analyzed.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN722

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本文編號：1644592