本文選題：時序優(yōu)化　切入點：數(shù)�；旌�　出處：《華中科技大學》2015年碩士論文　論文類型：學位論文

【摘要】：集成電路后端設計是指將已完成驗證的前端代碼設計轉化為可用于生產(chǎn)制造的物理版圖文件,是連接芯片設計與芯片制造的重要環(huán)節(jié)。其具體工作流程為:將前端設計代碼基于某一種生產(chǎn)工藝進行邏輯綜合、布局布線、時序分析及物理驗證,最終得到功耗和時序符合設計要求并可以進行流片的版圖文件。本文介紹了嵌入PLL(鎖相環(huán))大模板卷積ASIC的物理設計過程,著重解決了PLL的調(diào)用和數(shù)�；旌闲酒瑫r序優(yōu)化、布局布線及物理驗證等問題�？偟脑O計流程為:首先,建立PLL的物理模型,實現(xiàn)后端設計過程中調(diào)用;其次,在頂層代碼加入PLL數(shù)字控制邏輯,定義互聯(lián)關系并分析接口時序信息,完成物理綜合;然后,對嵌入PLL的數(shù)模混合版圖進行布局規(guī)劃,電源規(guī)劃,時鐘樹綜合,布線優(yōu)化;最后,對生成的版圖文件進行物理規(guī)則驗證。在時序優(yōu)化上,考慮PLL嵌入問題,根據(jù)互連信息分析PLL嵌入路徑時序。由于PLL模擬IP沒有詳細的內(nèi)部時序文件,所以對嵌入路徑時序約束時,整體考慮PLL的啟動參數(shù),以保證芯片的時序約束的合理性。在PLL物理模型建立上,首先根據(jù)數(shù)�；旌显O計要求,對原芯片版圖進行IP化修改,然后抽取該物理版圖的lef文件,最后通過IP版圖文件和LEF信息創(chuàng)建物理模型,以實現(xiàn)ASIC布局規(guī)劃時對PLL模擬IP的調(diào)用。在布局規(guī)劃上,區(qū)別于傳統(tǒng)數(shù)字后端的布局流程。首先根據(jù)數(shù)模接口的連線問題和模擬IP物理信息,確定嵌入PLL的擺放位置,然后對數(shù)模混合版圖相鄰位置進行隔離處理,阻止噪聲傳播,以實現(xiàn)對電路的靜電保護。最后對數(shù)字部分進行合理的布局規(guī)劃。完成布局布線設計后,得到一個低功耗和時序最優(yōu)的版圖文件,對該文件進行物理驗證以保證其符合生產(chǎn)設計規(guī)則。然后,將完成驗證的版圖數(shù)據(jù)進行后功能仿真。最終版圖仿真結果表明,芯片最高工作時鐘125MHz,功耗647mw,管腳數(shù)目97,面積3.742mm*3.746mm,能夠以40*32*8bit模板對512*512*8bit@110幀圖像進行實時卷積運算,輸出結果位寬27bit,芯片數(shù)據(jù)通過率達到230Mb/s,實現(xiàn)了預定技術指標。目前該設計已經(jīng)提交流片。
[Abstract]:Integrated circuit back-end design refers to the conversion of a verified front-end code design into a physical layout file that can be used in production and manufacturing. It is an important link between chip design and chip manufacturing. Its specific work flow is: the front-end design code is based on a certain production process for logic synthesis, layout and wiring, timing analysis and physical verification, Finally, the power consumption and timing can meet the design requirements and the layout file of the streaming chip can be carried out. This paper introduces the physical design process of embedded PLL (PLL) large template convolutional ASIC, and emphatically solves the call of PLL and the timing optimization of digital-analog hybrid chip. Layout, routing and physical verification. The overall design flow is as follows: firstly, the physical model of PLL is established to realize the call in the back-end design process; secondly, the PLL digital control logic is added to the top-level code. Define interconnections and analyze interface timing information to complete physical synthesis. Then, layout planning, power planning, clock tree synthesis, routing optimization of digital-analog mixed layout embedded in PLL. To verify the physical rules of the generated layout file. In timing optimization, considering the PLL embedding problem, analyzing the PLL embedded path timing according to the interconnection information. Because the PLL simulation IP does not have the detailed internal timing file, So when we embed path timing constraints, we should consider the starting parameters of PLL as a whole to ensure the rationality of timing constraints. In the establishment of PLL physical model, the original chip layout is modified by IP according to the requirement of mixed digital-analog design. Then the lef file of the physical layout is extracted, and finally the physical model is created by IP layout file and LEF information, so as to realize the call to PLL to simulate IP in the ASIC layout planning. The layout flow is different from the traditional digital back-end. Firstly, according to the connection problem of digital-analog interface and the physical information of analog IP, the location of embedded PLL is determined, and then the adjacent position of digital-analog mixed layout is isolated to prevent the noise from spreading. In order to achieve electrostatic protection of the circuit. Finally, the digital part of the reasonable layout planning. After the completion of the layout and wiring design, a low power consumption and timing optimal layout file, The physical verification of the file is carried out to ensure that it conforms to the production design rules. Then, the post-functional simulation of the completed layout data is carried out. The final layout simulation results show that, The highest working clock of the chip is 125 MHz, the power consumption is 647 MW, the number of pins is 97, and the area is 3.742mm / 3.746mm. The chip can perform real-time convolution operation on 512121212bit 8bit @ 110 frame image with 40m 32mm 8bit template. The output result is 27 bit wide and the pass rate of chip data is 230 MB / s, which has achieved the predetermined technical target.
【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

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