本文選題：擁塞　切入點(diǎn)：拓?fù)浣Y(jié)構(gòu)　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：世界數(shù)字化進(jìn)程的不斷推進(jìn)對(duì)集成電路的性能提出了更高的要求。集成電路仍以摩爾定律迅猛發(fā)展,單芯片上集成的晶體管數(shù)量不斷增加。集成電路中功能的集成化使得大量由不同設(shè)計(jì)公司與廠商的設(shè)計(jì)模塊(IP核)以SoC的設(shè)計(jì)方法被集成在單芯片上。各IP核之間通過(guò)信息交換和數(shù)據(jù)處理完成用戶所要求的系統(tǒng)功能。共享總線之類的長(zhǎng)的全局互連通信形式不能適應(yīng)眾多IP之間對(duì)于更高通信性能的需求,這使得數(shù)字系統(tǒng)的性能越來(lái)越受到通信能力的限制。片上網(wǎng)絡(luò)(NoC,Network-on-Chip)是多核SoC中的通信結(jié)構(gòu),負(fù)責(zé)眾多IP核之間的通訊。它來(lái)源于Internet中的分布式路由,通訊節(jié)點(diǎn)與數(shù)據(jù)鏈路由眾多用戶所共享,具有帶寬高、功耗低、易于擴(kuò)展的特點(diǎn)。本文針對(duì)二維Mesh結(jié)構(gòu)片上網(wǎng)絡(luò)的擁塞問(wèn)題進(jìn)行了研究,分別從拓?fù)浣Y(jié)構(gòu)、路由算法、數(shù)據(jù)注入控制三個(gè)方面對(duì)片上網(wǎng)絡(luò)進(jìn)行改進(jìn),以緩解網(wǎng)絡(luò)中的擁塞。首先,分析了二維Mesh結(jié)構(gòu)片上網(wǎng)絡(luò)的不足設(shè)計(jì)了分流拓?fù)浣Y(jié)構(gòu),該結(jié)構(gòu)利用邊緣路由節(jié)點(diǎn)中未被使用的I/O端口,增加了數(shù)據(jù)通路以降低擁塞。所設(shè)計(jì)的重定向算法實(shí)現(xiàn)對(duì)分流拓?fù)浣Y(jié)構(gòu)中新增路徑的使用。其次,分析了二維Mesh結(jié)構(gòu)片上網(wǎng)絡(luò)路由節(jié)點(diǎn)擁塞信息,并基于轉(zhuǎn)彎模型和擁塞信息實(shí)現(xiàn)了自適應(yīng)性路由算法。最后,設(shè)計(jì)了數(shù)據(jù)注入控制邏輯,通過(guò)調(diào)整注入率減少擁塞。本文采用VerilogHDL完成了電路的RTL級(jí)設(shè)計(jì),設(shè)計(jì)完成后在Modelsim下對(duì)4×4規(guī)模的分流拓?fù)浣Y(jié)構(gòu)片上網(wǎng)絡(luò)進(jìn)行功能仿真,實(shí)現(xiàn)了預(yù)期的功能。在標(biāo)準(zhǔn)測(cè)試平臺(tái)中以不同的流量模式對(duì)設(shè)計(jì)電路進(jìn)行了測(cè)試。與采用DOR算法的Mesh結(jié)構(gòu)片上網(wǎng)絡(luò)對(duì)比,本文設(shè)計(jì)的片上網(wǎng)絡(luò)在Random、Transpose1、Transpose2、Shuffle、Butterfly、Bit_reversal流量模式下的飽和吞率分別提升6.6%、25.6%、29.8%、14.8%、32.5%、23.5%。在SMIC 65nm工藝庫(kù)下綜合后表明,電路在300MHz時(shí)鐘頻率下能滿足時(shí)序要求。此時(shí)綜合網(wǎng)表面積為991Kμm2,與采用DOR算法的Mesh結(jié)構(gòu)片上網(wǎng)絡(luò)相比增加了4.5%。結(jié)果表明,本文設(shè)計(jì)的基于擁塞控制的片上網(wǎng)絡(luò)在性能提升的同時(shí)只增加了較少的硬件開(kāi)銷。
[Abstract]:The continuous progress of digitization in the world has put forward higher requirements for the performance of integrated circuits. Integrated circuits are still developing rapidly with Moore's law. The number of transistors integrated on a single chip has been increasing. The integration of functions in integrated circuits has led to a large number of IP cores from different design companies and manufacturers) being integrated on a single chip by the method of SoC. Long global interconnect communication forms such as shared bus can not meet the needs of many IP for higher communication performance. This makes the performance of digital system more and more limited by the communication ability. The network on chip (NOC) is a communication structure in multi-core SoC, which is responsible for the communication between many IP cores. It comes from the distributed routing in Internet. Communication nodes and data links are shared by many users, with the characteristics of high bandwidth, low power consumption and easy expansion. In order to alleviate the congestion in the network, the data injection control is improved in three aspects. Firstly, the insufficiency of the two-dimensional Mesh on-chip network is analyzed and the shunt topology is designed. This structure uses the unused I / O port in the edge routing node to increase the data path to reduce congestion. The proposed redirection algorithm realizes the use of the new path in the shunt topology. The congestion information of network routing nodes on a two-dimensional Mesh structure is analyzed, and the adaptive routing algorithm is implemented based on the turning model and congestion information. Finally, the data injection control logic is designed. By adjusting the injection rate to reduce congestion, this paper uses VerilogHDL to complete the RTL level design of the circuit. After the design is completed, the 4 脳 4 scale shunt topology on-chip network is simulated under Modelsim. The design circuit is tested in different flow modes on the standard test platform, and compared with the Mesh structure using DOR algorithm. The saturated swallowing rate of the network designed in this paper under the Random-transpose 1 / transpose _ 2Shuffle2 / Butterfly/ Bitreversal flow mode is increased by 6.6and 25.6g / 25.629.8B / 32.5g / 23.5respectively. It is shown by the synthesis under the SMIC 65nm process library that, The circuit can meet the timing requirements at 300MHz clock frequency. The integrated network surface area is 991K 渭 m ~ 2, which is 4.5 more than that of the Mesh structure using DOR algorithm. The results show that, The congestion control-based on-chip network designed in this paper increases the performance of the network with less hardware overhead.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47

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本文編號(hào)：1637711