本文選題：多模多標準　切入點：頻率綜合器　出處：《東南大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著各種無線通信模式的不斷涌現(xiàn),在一個移動終端上集成多種通信模式已成為當前無線通信技術(shù)發(fā)展的趨勢,支持多模多標準的無線射頻收發(fā)機也因此成為了人們研究的熱點。作為無線收發(fā)機射頻前端的關(guān)鍵模塊,頻率綜合器不僅決定了整個收發(fā)機性能的好壞,也是實現(xiàn)多模多標準無線收發(fā)機全集成的關(guān)鍵之一。小數(shù)分頻器通過改變分頻比使頻率綜合器能提供多個高精度頻率信號,是小數(shù)頻率綜合器中非常重要的模塊。本文對多模多標準系統(tǒng)中鎖相環(huán)頻率綜合器的小數(shù)分頻器進行研究和設(shè)計。本文首先介紹了小數(shù)頻率綜合器的基本原理和組成模塊,分析了各項性能指標,建立了鎖相環(huán)頻率綜合器鎖定狀態(tài)的線性相位模型,給出了各模塊到鎖相環(huán)頻率綜合器輸出端的噪聲傳遞函數(shù)。根據(jù)系統(tǒng)要求給出了頻率綜合器的系統(tǒng)架構(gòu)。在此基礎(chǔ)上,設(shè)計了一款小數(shù)分頻器,主要模塊包括高速二分頻器、0.5步進可編程分頻器與△-Σ調(diào)制器。第一級高速二分頻器工作在最高頻率,電路采用源極耦合邏輯實現(xiàn),具有很寬的頻率工作范圍。0.5步進可編程分頻器由第二級高速二分頻器、相位切換電路、整數(shù)可編程分頻器與邏輯控制模塊構(gòu)成。其中,第二級高速二分頻器輸出四路正交信號,供相位切換電路進行切換；整數(shù)可編程分頻器由6級2/3分頻器級聯(lián)構(gòu)成,通過加入邏輯門進行分頻比擴展,可實現(xiàn)32～127的分頻比范圍。邏輯控制模塊通過控制相位切換的次數(shù)來實現(xiàn)0.5的分頻比步進�！�-Σ調(diào)制器采用了一種改進的MASH 1-1-1結(jié)構(gòu)實現(xiàn),它由三個一階誤差反饋調(diào)制器級聯(lián)而成,與傳統(tǒng)結(jié)構(gòu)的MASH 1-1-1結(jié)構(gòu)相比,本設(shè)計中第二級與第三級的誤差反饋調(diào)制器之間增加了一個前饋連接,可同時接收前級的量化噪聲和最終輸出,可以提高輸出序列長度以減小小數(shù)雜散,△-Σ調(diào)制器采用數(shù)字半定制方法實現(xiàn)。該小數(shù)分頻器采用TSMC 0.18μm RF CMOS工藝設(shè)計。整個小數(shù)分頻器的面積為1130μm×510μm,已成功流片,并且完成在片測試,測試結(jié)果表明：在1.8V電源電壓下,小數(shù)分頻器在0.8-9GHz頻率范圍內(nèi)能夠正確分頻,分頻比范圍達到62.5～254,總的電流消耗為29mA,滿足指標要求。本論文所設(shè)計的多模多標準小數(shù)分頻器在無線通信、衛(wèi)星導(dǎo)航、無線傳感網(wǎng)等領(lǐng)域都具有應(yīng)用價值,應(yīng)用前景廣闊,并對其他應(yīng)用設(shè)計也具有一定的參考意義。
[Abstract]:With the emergence of various wireless communication modes, the integration of multiple communication modes on a mobile terminal has become the trend of the development of wireless communication technology. As a key module of RF front end of wireless transceiver, frequency synthesizer not only determines the performance of the whole transceiver. It is also one of the keys to realize the full integration of multi-mode and multi-standard wireless transceiver. The fractional frequency divider can provide multiple high-precision frequency signals by changing the frequency divider ratio. It is a very important module in decimal frequency synthesizer. This paper studies and designs the fractional frequency divider of PLL frequency synthesizer in multi-mode and multi-standard system. Firstly, this paper introduces the basic principle and composing module of decimal frequency synthesizer. The performance indexes are analyzed, and the linear phase model of the locked state of PLL frequency synthesizer is established. The noise transfer function from each module to the output of the PLL frequency synthesizer is given. The system architecture of the frequency synthesizer is given according to the system requirements. On this basis, a fractional frequency divider is designed. The main modules include a high speed dicusser, a 0.5 step programmable frequency divider and a-危 modulator. The first stage high speed frequency divider operates at the highest frequency, and the circuit is realized by source pole coupling logic. The step programmable frequency divider has a wide frequency range. 0.5 step programmable frequency divider consists of a second stage high speed two frequency divider, a phase switching circuit, an integer programmable frequency divider and a logic control module, in which the second stage high speed second frequency divider outputs four orthogonal signals. The integer programmable frequency divider is composed of 6 stages 2/3 frequency divider cascaded, and the frequency division ratio is expanded by adding logic gate. The logic control module realizes the frequency division ratio step of 0.5 by controlling the frequency of phase switching. The-危 modulator is implemented by an improved MASH 1-1-1 structure, which consists of three first-order error feedback modulators cascaded. Compared with the traditional MASH 1-1-1 structure, a feedforward connection is added between the second stage and the third stage of the error feedback modulator in this design, which can receive both the quantized noise and the final output of the previous stage. The output sequence length can be increased to reduce the fractional spurious, and the-危 modulator is realized by digital semi-customization. The fractional frequency divider is designed by TSMC 0.18 渭 m RF CMOS process. The area of the whole fractional frequency divider is 1130 渭 m 脳 510 渭 m. The test results show that the fractional frequency divider can divide the frequency correctly in the frequency range of 0.8-9GHz at 1.8 V power supply voltage. The frequency division ratio reaches 62.5? 254and the total current consumption is 29mA. the multi-mode and multi-standard fractional frequency divider designed in this paper has great application value in wireless communication, satellite navigation, wireless sensor network and so on. And also has certain reference significance to other application design.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN772

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