本文選題：SOC　切入點：IP軟核　出處：《蘭州大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路技術(shù)的高速發(fā)展,SOC技術(shù)已經(jīng)越來越多的得到關(guān)注和應(yīng)用,尤其是片上總線技術(shù)和IP技術(shù)的出現(xiàn)使其逐漸成為IC設(shè)計的主流技術(shù)。但是目前SOC的發(fā)展也面臨巨大挑戰(zhàn),主要是IP復(fù)用技術(shù)和IP互連技術(shù),因此研究IP復(fù)用技術(shù)對于SOC發(fā)展具有重要意義。SPI是Motorola公司開發(fā)的一種同步、高速、全雙工的通信總線,因其信號線少、結(jié)構(gòu)簡單等特點被越來越多的芯片集成為通信總線�；诖�,本文設(shè)計了兩種可復(fù)用、可配置的SPI協(xié)議IP軟核,為SOC設(shè)計中的IP互連提供靈活的SPI接口,這完全滿足SOC技術(shù)的發(fā)展要求和發(fā)展方向,對于業(yè)界和SPI的推廣應(yīng)用都具有極高的意義和實用價值。論文采用自頂向下的設(shè)計思路設(shè)計了兩種可復(fù)用的SPI協(xié)議IP軟核。其中基于微控制器的SPI協(xié)議IP軟核的設(shè)計主要關(guān)注SPI主機功能,制定了設(shè)計目標,使其可與8個從機通信,同時能設(shè)置通信速率和選擇傳輸模式,并將接收邏輯和發(fā)送邏輯分開,為發(fā)送和接收數(shù)據(jù)設(shè)計了雙緩沖機制。根據(jù)設(shè)計目標劃分了子模塊并給出了完整的模塊問互連框圖,說明了寄存器設(shè)置,論述了關(guān)鍵子模塊的Verilog HDL實現(xiàn)過程,包括設(shè)計思路分析,微控制器接口模塊、時鐘邏輯模塊以及發(fā)送和接收邏輯模塊的Verilog代碼設(shè)計和其中關(guān)鍵問題的解決方法。之后設(shè)計了一種基于Wishbone總線的SPI協(xié)議IP軟核。該IP軟核通過參數(shù)化的方法實現(xiàn)設(shè)備數(shù)量為4、8、16時多設(shè)備間的通信,并自主決定設(shè)備的主從身份,通過設(shè)置對從機控制的優(yōu)先級別仲裁多主設(shè)備對同一從機的控制權(quán)。同時能靈活設(shè)置通信模式和通信速率。分析以上設(shè)計目標并劃分了功能子模塊,說明了寄存器的設(shè)置過程,最后詳細闡述了關(guān)鍵子模塊的Verilog HDL實現(xiàn)過程,包括整體的設(shè)計思路和Wishbone總線接口模塊、時鐘邏輯模塊以及內(nèi)部控制寄存器模塊的功能分析和Verilog代碼設(shè)計。在完成設(shè)計的基礎(chǔ)上,采用業(yè)界認可的仿真軟件Modelsim和QuartusⅡ?qū)υO(shè)計的兩種IP軟核分別進行了RTL級功能和時序仿真驗證,結(jié)果表明兩種SPI協(xié)議IP軟核設(shè)計正確,所有功能都達到預(yù)期的目標,仿真驗證順利通過。
[Abstract]:With the rapid development of integrated circuit technology, SOC technology has been paid more and more attention and application. Especially the emergence of on-chip bus technology and IP technology make them become the mainstream technology in IC design. However, the development of SOC is also facing great challenges, mainly IP multiplexing technology and IP interconnection technology. Therefore, the study of IP multiplexing technology is of great significance for the development of SOC. SPI is a synchronous, high-speed, full-duplex communication bus developed by Motorola Company, because of its few signal lines. The simple structure has been integrated into communication bus by more and more chips. Based on this, two reusable and configurable SPI protocol IP soft cores are designed to provide flexible SPI interface for IP interconnection in SOC design. This fully meets the development requirements and development direction of SOC technology. It is of great significance and practical value for the industry and the popularization and application of SPI. In this paper, two reusable SPI protocol IP soft cores are designed by using top-down design idea. Among them, SPI protocol IP soft core based on microcontroller is designed. The design focuses on the SPI host function, A design goal has been set so that it can communicate with eight slave computers, set the communication rate and select the transmission mode, and separate the receiving logic from the transmission logic. A double buffer mechanism is designed for sending and receiving data. According to the design objective, the sub-modules are divided and the complete block diagram of module interconnect is given. The register setting is explained, and the Verilog HDL implementation process of the key sub-modules is discussed. Including design thinking analysis, microcontroller interface module, The Verilog code design of the clock logic module and the sending and receiving logic module and the solution of the key problems are also presented. Then, a SPI protocol IP soft core based on Wishbone bus is designed. The IP soft core is realized by parameterization method. The number of equipment is 4 / 8, and the communication between more than 16:00 devices, And independently determine the master-slave status of the device, By setting the priority control of the slave to arbitrate the control over the same slave, the communication mode and the communication rate can be set flexibly. The above design objectives are analyzed and the functional sub-modules are divided, and the process of setting up the register is explained. Finally, the Verilog HDL implementation process of the key sub-modules is described in detail, including the whole design idea and the Wishbone bus interface module, the function analysis of the clock logic module and the internal control register module, and the Verilog code design. Two kinds of IP soft cores designed are verified by RTL level and time sequence simulation using Modelsim and Quartus 鈪，

本文編號：1593284