本文選題：憶阻器　切入點(diǎn)：RRAM　出處：《電子科技大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路工藝的不斷演進(jìn),FPGA的集成度越來越高,功耗、面積及制造成本等與ASIC之間的差距越來越小,加之在動(dòng)態(tài)可重構(gòu)領(lǐng)域的優(yōu)勢(shì),使其大有替代ASIC成為數(shù)字電路設(shè)計(jì)主要載體的趨勢(shì)。然而,現(xiàn)今主流SRAM型FPGA使用掉電丟失數(shù)據(jù)的SRAM存儲(chǔ)配置信息,上電時(shí)需要從片外非易失存儲(chǔ)芯片如PROM或FLASH載入配置位流,使得這種FPGA的配置信息容易被竊取。PROM和FLASH占據(jù)了相當(dāng)?shù)陌寮?jí)面積,還增加了電路系統(tǒng)的尺寸。針對(duì)SRAM型FPGA存在的上述問題,本文從向SRAM型FPGA中集成憶阻器的角度提出了一種解決方案。憶阻器是一種新型存儲(chǔ)器件,它具有非易失性和可重復(fù)編程性,還兼容標(biāo)準(zhǔn)CMOS工藝。利用憶阻器這一優(yōu)點(diǎn),本文將憶阻器與SRAM相結(jié)合,得到了一種ReSRAM編程點(diǎn)。基于這種編程點(diǎn)的阻變FPGA配置信息的安全性大大增強(qiáng)并能夠快速上電啟動(dòng),配置存儲(chǔ)陣列能夠被逐幀配置。本文還設(shè)計(jì)了基于這種編程點(diǎn)的非易失性查找表和可編程開關(guān)電路,以及針對(duì)阻變FPGA的編程通道與配置流程。本文使用基于憶阻器導(dǎo)電細(xì)絲原理的Verilog-AMS仿真模型和中芯國(guó)際0.13μm標(biāo)準(zhǔn)CMOS邏輯工藝庫(kù),在Cadence的AMS仿真平臺(tái)下對(duì)文中的電路進(jìn)行仿真驗(yàn)證。仿真與理論分析的結(jié)果表明:本文所設(shè)計(jì)的查找表能夠完全兼容SRAM FPGA的查找表,而可編程開關(guān)的延遲也與SRAM型FPGA可編程開關(guān)的延遲沒有任何區(qū)別,所設(shè)計(jì)的編程通道能夠?qū)eSRAM編程點(diǎn)進(jìn)行類似SRAM的回讀和寫入操作。這樣就可以使用成熟的SRAM FPGA布局布線CAD軟件,使阻變FPGA具有極高的兼容性和應(yīng)用價(jià)值。
[Abstract]:With the continuous evolution of integrated circuit technology, the integration of FPGA becomes more and more high, the gap between power consumption, area and manufacturing cost and ASIC becomes smaller and smaller, and the advantages in dynamic reconfigurable field. However, the current mainstream SRAM FPGA uses SRAM to store configuration information of power loss data, so it is necessary to load the configuration bit stream from off-chip non-volatile memory chips such as PROM or FLASH when power on. The configuration information of this kind of FPGA is easily stolen. Prom and FLASH occupy a considerable area of board, and increase the size of circuit system. In this paper, a solution is proposed from the point of view of integrating resistive devices into SRAM type FPGA, which is a new type of memory device. It has the advantages of non-volatile, repeatable programming and compatible with standard CMOS process. In this paper, a kind of ReSRAM programming point is obtained by combining the resistor with SRAM. The security of the resistive FPGA configuration information based on this programming point is greatly enhanced and can be started quickly. The configuration storage array can be configured frame by frame. This paper also designs a nonvolatile lookup table and a programmable switch circuit based on this programming point. And the programming channel and configuration flow of resistive FPGA. In this paper, the Verilog-AMS simulation model based on the principle of resistive conductive filament and the SMIC 0.13 渭 m standard CMOS logic process library are used. The circuit in this paper is simulated on the AMS platform of Cadence. The results of simulation and theoretical analysis show that the look-up table designed in this paper can be fully compatible with the SRAM FPGA lookup table. The delay of the programmable switch is no different from that of the SRAM type FPGA programmable switch. The designed programming channel can read and write the ReSRAM programming points like SRAM, so that the mature SRAM FPGA layout and routing CAD software can be used, which makes the resistive FPGA have high compatibility and application value.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN791

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本文編號(hào)：1588961