本文選題：功能驗(yàn)證　切入點(diǎn)：SVA　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路一直在向高性能、高集成度、低功耗的SoC方向發(fā)展,功能驗(yàn)證在設(shè)計(jì)開發(fā)過程中變得越來(lái)越復(fù)雜和越來(lái)越重要。傳統(tǒng)的驗(yàn)證技術(shù)和方法在開發(fā)周期,驗(yàn)證效率以及驗(yàn)證平臺(tái)的可觀性、可控性和可復(fù)用性等方面的表現(xiàn)已經(jīng)不能夠滿足當(dāng)前的需求。伴隨著電子設(shè)計(jì)自動(dòng)化技術(shù)的快速發(fā)展,各種各樣的新型的驗(yàn)證技術(shù)和方法就如何提高驗(yàn)證效率,縮短開發(fā)周期以及開發(fā)可移植的驗(yàn)證組件和環(huán)境等方面做了很多的探索,他們已經(jīng)在諸多方面彌補(bǔ)了傳統(tǒng)驗(yàn)證技術(shù)和方法的不足。本文基于斷言驗(yàn)證方法,主要研究了System Verilog Assertion的功能驗(yàn)證技術(shù)在實(shí)際項(xiàng)目中的應(yīng)用。根據(jù)SVA的語(yǔ)言與驗(yàn)證技術(shù)特點(diǎn),分析闡述了其在驗(yàn)證環(huán)境開發(fā)和使用過程中的優(yōu)勢(shì)。針對(duì)中斷延遲控制器,提出了一個(gè)單靠形式化方法的功能驗(yàn)證設(shè)計(jì)方案,根據(jù)其功能規(guī)范的要求,使用SVA編寫了用于斷言和假設(shè)的屬性,通過Jasper形式驗(yàn)證技術(shù),實(shí)現(xiàn)了驗(yàn)證平臺(tái)的搭建以及完成了該模塊的功能驗(yàn)證工作。該方法在保證驗(yàn)證質(zhì)量的同時(shí)有效的縮短了開發(fā)周期,提高了驗(yàn)證效率。另外,基于當(dāng)前流行的OVM驗(yàn)證方法學(xué)對(duì)通用輸入輸出控制模塊提出了一種斷言覆蓋率驅(qū)動(dòng)的驗(yàn)證設(shè)計(jì)方案,在OVM類庫(kù)的基礎(chǔ)上實(shí)現(xiàn)了用于待測(cè)設(shè)計(jì)的OVC組件,通過斷言模塊的功能檢測(cè)和覆蓋率分析搭建了一個(gè)完整的驗(yàn)證平臺(tái),實(shí)現(xiàn)了一個(gè)高層次化,高覆蓋率,可復(fù)用性強(qiáng)的驗(yàn)證環(huán)境。本文研究開發(fā)的驗(yàn)證環(huán)境和平臺(tái)成功的完成了待測(cè)設(shè)計(jì)的功能驗(yàn)證,并已經(jīng)應(yīng)用到實(shí)際的項(xiàng)目中。中斷延遲控制器的形式化驗(yàn)證方法已經(jīng)推廣到其他相似功能模塊的驗(yàn)證工作,通用輸入輸出控制模塊的驗(yàn)證組件和斷言模塊很好的復(fù)用到其他的項(xiàng)目。研究結(jié)果和實(shí)踐表明,基于SVA的驗(yàn)證技術(shù)和方法實(shí)現(xiàn)的形式驗(yàn)證環(huán)境的功能覆蓋率達(dá)到100%,并且有效地節(jié)省了開發(fā)時(shí)間,縮短了的驗(yàn)證周期;實(shí)現(xiàn)的OVM驗(yàn)證平臺(tái)具有很高的可復(fù)用性,并且其功能覆蓋率達(dá)到100%,代碼覆蓋率達(dá)到97.9%。
[Abstract]:With the development of integrated circuits in the direction of high performance, high integration and low power consumption, functional verification has become more and more complex and important in the process of design and development. The performance of verification efficiency and the observability, controllability and reusability of the verification platform can no longer meet the current needs. With the rapid development of electronic design automation technology, Various new verification technologies and methods have done a lot of research on how to improve the efficiency of verification, shorten the development cycle and develop portable verification components and environments. They have made up for the shortcomings of traditional verification techniques and methods in many aspects. Based on the assertion verification method, this paper mainly studies the application of System Verilog Assertion function verification technology in actual projects. According to the characteristics of SVA language and verification technology, This paper analyzes and expounds its advantages in the process of developing and using the verification environment. For interrupt delay controller, a design scheme of function verification based on formal method is proposed, according to the requirements of its function specification. The attributes used for assertion and hypothesis are written with SVA, and the verification platform is built and the function verification work of the module is completed by means of Jasper formal verification technology. This method can effectively shorten the development period while guaranteeing the verification quality. In addition, based on the popular OVM verification methodology, an assertion coverage driven verification design scheme is proposed for the general input and output control module. Based on the OVM class library, a OVC component is implemented for the design to be tested. Through the function detection and coverage analysis of the assertion module, a complete verification platform is built, which realizes a high level and high coverage. The verification environment and platform developed in this paper have successfully completed the functional verification of the design to be tested. The formal verification method of interrupt delay controller has been extended to other similar functional modules. The verification components and assertion modules of the Universal I / O control module are well reused to other projects. The function coverage of formal verification environment based on SVA is 100, and the development time is saved and the verification cycle is shortened. The OVM verification platform has high reusability. And its function coverage rate reaches 100%, the code coverage rate reaches 97.9%.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407

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本文編號(hào)：1588722