本文選題：軟錯誤　切入點：加固鎖存器　出處：《合肥工業(yè)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：在集成電路制造水平不斷發(fā)展的當(dāng)下,芯片的集成度越來越高,工作頻率越來越快,工作電壓和晶體管的閾值電壓不斷降低,晶體管尺寸也在逐年減小,所以芯片電路內(nèi)部節(jié)點臨界電荷量也在持續(xù)的減少,導(dǎo)致電路軟錯誤率不斷上升。由于目前軟錯誤對于集成電路影響日益加劇,針對已有的鎖存器電路結(jié)構(gòu)方案所存在的缺陷,設(shè)計了一個新的高速低功耗的加固鎖存器結(jié)構(gòu)。其中提出了一個新的C單元連接方法,大大降低了鎖存模塊的短路功耗;對輸出級C單元進行改進,其自身內(nèi)部節(jié)點的臨界電荷量得到加強,并且穩(wěn)固了輸出節(jié)點的值,使其在輸入端受到攻擊時不會處于高阻狀態(tài),從而提升了鎖存器整體的抗軟錯誤能力。通過HSPICE在22nm預(yù)測模型下進行仿真,驗證了該結(jié)構(gòu)的可靠性,并與已有的一些優(yōu)秀的抗軟錯誤鎖存器結(jié)構(gòu)進行對比。實驗結(jié)果顯示了本文設(shè)計的鎖存器犧牲了 25.78%的晶體管數(shù)目,來換取功耗、延遲、以及抗軟錯誤性能方面的提升;功耗、延遲分別平均降低43.12%、46.25%,功耗延遲積降低了 37.61%～97.50%,平均值達到68.98%,可以說本設(shè)計在具有很高的可靠性的同時,功耗、延遲等指標(biāo)也有大幅提升。
[Abstract]:At present, with the development of IC manufacturing level, the integration of chips is getting higher and higher, the working frequency is faster and faster, the operating voltage and the threshold voltage of transistors are decreasing, and the size of transistors is decreasing year by year. Therefore, the critical charge of the internal nodes of the chip circuit is also decreasing, which leads to the increasing soft error rate of the circuit. Because of the increasing influence of the soft error on the integrated circuit at present, the defects of the existing latch circuit structure are pointed out. A new high speed and low power reinforced latch structure is designed, in which a new C unit connection method is proposed, which greatly reduces the short circuit power consumption of the latch module, and improves the output level C unit. The critical charge of its own internal node is strengthened and the output node is stabilized so that it will not be in a high resistance state when the input is attacked. Thus, the overall anti-soft error capability of the latch is improved. The reliability of the structure is verified by HSPICE simulation under the 22nm prediction model. The experimental results show that the designed latch has sacrificed 25.78% transistors in exchange for power consumption, delay, and anti-soft error performance. The average delay is reduced by 43.12and 46.25, the power delay product is reduced by 37.61 and 97.50, the average value is up to 68.98. It can be said that the design has high reliability, and the power consumption, delay and other indexes are also greatly improved.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN40

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本文編號：1564119