發(fā)布時(shí)間：2018-03-02 13:52

  本文選題：應(yīng)變Ge　切入點(diǎn)：NMOS　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著微電子技術(shù)的發(fā)展,晶體管的特征尺寸越來越小,集成電路的規(guī)模也越來越大,采用傳統(tǒng)的等比例縮小原則提升集成電路性能的方法越來越受到物理與工藝的限制,制約了集成電路性能的進(jìn)一步發(fā)展。應(yīng)變Ge材料與技術(shù)具有載流子遷移率高、能帶可調(diào)且與成熟的硅工藝兼容的優(yōu)勢,成為了延續(xù)摩爾定律進(jìn)一步發(fā)展的有效途徑。本文重點(diǎn)研究了應(yīng)變Ge材料載流子有效質(zhì)量、散射幾率和遷移率等關(guān)鍵物理參數(shù)隨應(yīng)力強(qiáng)度、晶面的變化規(guī)律,以及應(yīng)變Ge材料性能增強(qiáng)機(jī)制,分析比較了應(yīng)變Ge MOS器件溝道應(yīng)力引入機(jī)制,提出了適于集成電路工藝的溝道應(yīng)力引入方法;研究了應(yīng)變Ge MOS的界面特性,分析了界面態(tài)生成的機(jī)制和柵漏電機(jī)制,優(yōu)化了柵介質(zhì)的結(jié)構(gòu),獲得了優(yōu)化的柵結(jié)構(gòu)及其制備方法;在以上研究的基礎(chǔ)上,本文提出采用多數(shù)載流子形成導(dǎo)電溝道的新型應(yīng)變Ge NMOS結(jié)構(gòu),有效地解決了摻雜元素硼(B)在Ge中激活率和p型Ge載流子遷移率低的問題;為了獲得更高的器件電流開關(guān)比,進(jìn)一步地提出了基于GOI的凹槽柵極應(yīng)變Ge NMOS結(jié)構(gòu),該結(jié)構(gòu)非常易于集成;通過仿真軟件,研究了溝道長度、柵極凹槽角度和深度等幾何結(jié)構(gòu)參數(shù)對該器件閾值電壓、開態(tài)電流、開關(guān)比等電學(xué)特性的影響;定量地分析了溝道摻雜、柵極介電常數(shù)等物理參數(shù)對器件電學(xué)特性的影響,揭示了電學(xué)特性隨幾何結(jié)構(gòu)、物理參數(shù)參數(shù)的演化規(guī)律,獲得了優(yōu)化的器件結(jié)構(gòu)、物理參數(shù);給出了優(yōu)化的凹槽柵極應(yīng)變Ge NMOS器件工藝實(shí)現(xiàn)方法,并進(jìn)行了模擬仿真,結(jié)果表明,柵極氧化層應(yīng)選用高介電常數(shù)的high-K材料,且從開關(guān)比的角度考慮厚度為5nm最為合適;柵極金屬功函數(shù)應(yīng)盡量的大以獲得更大的器件開關(guān)比;柵極凹槽角度較小時(shí),器件關(guān)態(tài)電流IOFF會較大,從而降低器件的開關(guān)比;最后,提出了應(yīng)用于集成電路的柵極凹槽應(yīng)變Ge CMOS,形成了反向器單元,仿真結(jié)果表明,在輸入輸出擺幅為2V時(shí),高噪聲容限為0.933V,低噪聲容限為0.973V。為高性能應(yīng)變Ge的集成電路的發(fā)展提供了理論支撐。
[Abstract]:With the development of microelectronic technology, the characteristic size of transistors becomes smaller and smaller, and the scale of integrated circuits becomes larger and larger. Strain GE materials and technologies have the advantages of high carrier mobility, tunable band and compatible with mature silicon processes. In this paper, the key physical parameters, such as effective mass of carrier, scattering probability and mobility of strained GE materials, are studied with stress intensity and crystal plane. The mechanism of strain GE material performance enhancement is analyzed and compared, the channel stress introduction method suitable for integrated circuit process is proposed, the interface characteristics of strain GE MOS are studied, the mechanism of channel stress introduction in strain GE MOS device is analyzed and compared, and the channel stress introduction method suitable for integrated circuit process is proposed. The mechanism of interface state generation and gate leakage are analyzed, the structure of gate dielectric is optimized, and the optimized gate structure and its preparation method are obtained. In this paper, a new strain GE NMOS structure with conducting channels formed by majority carriers is proposed, which can effectively solve the problem of low activation rate and p type GE carrier mobility in GE doped with boron B, in order to obtain a higher current-switching ratio. Furthermore, a grooved gate strain GE NMOS structure based on GOI is proposed, which is very easy to integrate, and the threshold voltage and open current of the device are studied by the simulation software, such as channel length, gate groove angle and depth, etc. The influence of the physical parameters such as channel doping, gate dielectric constant and other physical parameters on the electrical properties of the device is analyzed quantitatively, and the evolution law of the electrical characteristics with the geometric structure and the physical parameters is revealed. The optimized device structure and physical parameters are obtained, and the method of realizing the optimized gate strain GE NMOS device process is given, and the simulation results show that the gate oxide layer should be made of high-K material with high dielectric constant. Considering the thickness of 5 nm from the angle of switching ratio, the gate metal work function should be as large as possible in order to obtain a larger switch ratio, and when the angle of gate groove is small, the switching current IOFF of the device will be larger, thus reducing the switching ratio of the device. Finally, the grid grooves strain GE CMOSs used in integrated circuits are proposed, and the inverters are formed. The simulation results show that, when the input and output swing is 2V, The high noise tolerance is 0.933 V and the low noise tolerance is 0.973V. it provides theoretical support for the development of high performance strained GE integrated circuits.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386

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相關(guān)碩士學(xué)位論文 前1條

1 劉翔宇;新型凹槽柵極應(yīng)變Ge NMOS器件設(shè)計(jì)與特性研究[D];西安電子科技大學(xué);2015年

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本文編號：1556802