本文關(guān)鍵詞： 集成化 硅磁敏三極管差分結(jié)構(gòu) MEMS技術(shù) 磁靈敏度 溫度系數(shù)　出處：《黑龍江大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：本文在分析立體結(jié)構(gòu)硅磁敏三極管基本結(jié)構(gòu)、工作原理和特性基礎(chǔ)上,給出集成化硅磁敏三極管差分結(jié)構(gòu),該集成化結(jié)構(gòu)由兩個(gè)相反磁敏感方向的硅磁敏三極管(T-1管和T-2管)和集電極負(fù)載電阻構(gòu)成,包括一個(gè)發(fā)射極(E)、兩個(gè)基極(B1、B2)、兩個(gè)集電極(C1、C2)和兩個(gè)集電極負(fù)載電阻(RL1、RL2)。理論分析給出,該結(jié)構(gòu)能夠?qū)崿F(xiàn)外加磁場(chǎng)測(cè)量且磁靈敏度得到提高,根據(jù)基本結(jié)構(gòu),采用ATLAS軟件構(gòu)建硅磁敏三極管差分結(jié)構(gòu)仿真模型,分別研究基區(qū)長(zhǎng)度L和基區(qū)寬度w對(duì)集成化硅磁敏三極管差分結(jié)構(gòu)磁特性的影響,實(shí)現(xiàn)結(jié)構(gòu)尺寸優(yōu)化�；谏鲜�,本文采用MEMS技術(shù)在P型100晶向雙面拋光高阻單晶硅襯底上制作硅磁敏三極管差分結(jié)構(gòu)集成化芯片。室溫條件下,通過采用半導(dǎo)體特性分析系統(tǒng)(KEITHLEY 4200)、磁場(chǎng)發(fā)生器系統(tǒng)(CH-1)和高低溫試驗(yàn)箱(奧貝斯GDJS-100LG-G),分別對(duì)單個(gè)硅磁敏三極管和硅磁敏三極管差分結(jié)構(gòu)集成化芯片進(jìn)行IC-VCE特性、磁特性和溫度特性測(cè)試。當(dāng)VDD=10.0 V,IB=8.0 mA時(shí),基區(qū)長(zhǎng)度L為150μm的單個(gè)硅磁敏三極管和硅磁敏三極管差分結(jié)構(gòu)集成化芯片的集電極電壓絕對(duì)磁靈敏度分別為259 mV/T和443mV/T,集電極電壓相對(duì)溫度系數(shù)分別為116.0 ppm/℃和54.4 ppm/℃,實(shí)驗(yàn)結(jié)果表明硅磁敏三極管集成化差分結(jié)構(gòu)可以提高磁靈敏度和改善溫度特性。在此基礎(chǔ)上,研究基區(qū)長(zhǎng)度對(duì)集成化芯片IC-VCE特性和磁特性的影響,當(dāng)VDD=6.0 V,IB=8.0 mA時(shí),基區(qū)長(zhǎng)度分別為120μm、150μm和180μm硅磁敏三極管差分結(jié)構(gòu)集成化芯片集電極電壓絕對(duì)磁靈敏度為435 mV/T、390 mV/T和327 mV/T,故基區(qū)長(zhǎng)度為120μm的集成化芯片具有較優(yōu)的磁敏特性。
[Abstract]:Based on the analysis of the basic structure, working principle and characteristics of the stereoscopic silicon magnetic sensing transistor, the differential structure of the integrated silicon magnetic sensing transistor is presented in this paper. The integrated structure consists of two silicon magnetically sensitive transistors in opposite directions: T-1 and T-2) and collector load resistors, including an emitter, two base electrodes, two base electrodes, two collector electrodes, two collector electrodes, two collector electrodes, and two collector loaded resistors, RL1 and RL2.The theoretical analysis shows that, The structure can realize the measurement of external magnetic field and the magnetic sensitivity is improved. According to the basic structure, the differential structure simulation model of silicon magnetic sensitive transistor is constructed by using ATLAS software. The effects of base length L and base width w on the magnetic characteristics of the differential structure of integrated silicon magnetic-sensitive transistor are studied respectively to optimize the structure size. In this paper, MEMS technology is used to fabricate the differential structure integrated silicon magnetic-sensitive transistor on P-type 100 crystal double-sided polished high resistance monocrystalline silicon substrate. At room temperature, the silicon magnetic-sensitive transistor is fabricated at room temperature. By using the semiconductor characteristic analysis system KEITHLEY 4200, the magnetic field generator system CH-1) and the high and low temperature test box (OBES GDJS-100LG-GN), the IC-VCE characteristics of the single silicon magnetic-sensitive transistor and the differential structure integrated chip of the silicon magnetic-sensitive transistor are carried out, respectively. Testing of magnetic and temperature characteristics. When the VDD=10.0 vane is 8.0 Ma, The collector voltage absolute magnetic sensitivity of a single silicon magnetic sensing transistor with a base length L of 150 渭 m and that of a differential integrated silicon magnetic transistor is 259 mV/T and 443 MV / T, respectively. The relative temperature coefficient of collector voltage is 116.0 ppm / 鈩，

本文編號(hào)：1554429