本文關(guān)鍵詞： ASIC 低功耗 數(shù)字加速度計(jì) Sigma-Delta　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著時(shí)代的發(fā)展與科技的進(jìn)步,微電子技術(shù)也逐漸融入到軍事、民用等各個(gè)領(lǐng)域中,其中數(shù)字加速度計(jì)憑借精度高,噪聲特性好,穩(wěn)定性高和功耗低等優(yōu)點(diǎn),被廣泛地運(yùn)用到軍事與民用的范疇。高性能的加速度計(jì)接口電路是保證加速度計(jì)穩(wěn)定工作的基礎(chǔ)。近年來,以智能手機(jī),平板電腦與可穿戴智能設(shè)備為代表的便攜式電子設(shè)備的快速發(fā)展與廣泛普及,智能設(shè)備的續(xù)航問題成為消費(fèi)者與設(shè)計(jì)者關(guān)注的焦點(diǎn),因此低功耗數(shù)字加速度計(jì)接口電路的研究具有重要的研究意義與實(shí)際價(jià)值。本文從數(shù)字加速度計(jì)的工作原理與系統(tǒng)結(jié)構(gòu)入手,對機(jī)械結(jié)構(gòu)敏感單元的工作過程與信號檢測的原理進(jìn)行分析,并選擇了方便低功耗設(shè)計(jì)的五階帶前饋結(jié)構(gòu)的分布式反饋加速度計(jì)系統(tǒng)結(jié)構(gòu),對其在Matlab的Simulink下建立包含運(yùn)放噪聲、kT/C噪聲、時(shí)鐘抖動(dòng)等非理想因素的行為級模型,得到的仿真結(jié)果為SNDR:101.5dB,ENOB:16.57dits。通過測試芯片的功耗來分析電路設(shè)計(jì)上可優(yōu)化的結(jié)構(gòu)問題。討論了在模擬電路中的低功耗設(shè)計(jì)方法,噪聲、動(dòng)態(tài)范圍等對功耗的限制,并對開關(guān)電容電路中的運(yùn)算放大器做詳細(xì)的功耗分析與低功耗設(shè)計(jì)。在理論與行為級的仿真的基礎(chǔ)上,基于0.5μm CMOS工藝,在Cadence下完成對五階低功耗數(shù)字加速度計(jì)接口電路的設(shè)計(jì)。Sigma-Delta數(shù)字加速度計(jì)接口電路系統(tǒng)的各個(gè)功能模塊均能正常工作。電源電壓為5V,仿真得到整體電路的功耗為9.4mW,量程為±2g,輸出信號的噪聲水平在-140dBV/Hz1/2,靈敏度320mV/g,等效輸入加速度噪聲0.8μg/Hz1/2。
[Abstract]:With the development of science and technology in the era of progress, microelectronic technology is gradually integrated into the military, civil and other fields, including digital accelerometer with high accuracy and good noise characteristics, high stability and low power consumption advantages, has been widely applied to military and civilian areas. High performance accelerometer interface circuit is the foundation to ensure the acceleration meter stability. In recent years, with the rapid development of intelligent mobile phone, tablet computer and smart wearable device for portable electronic devices and popularity of smart devices, battery life issues become the focus of attention of consumers and designers, so the research of low power digital accelerometer interface circuit has important significance and practical value. Starting with the working principle and system structure of the digital accelerometer, the principle and working process of signal detection of mechanical structure of the sensitive unit Analysis and selection of distributed five order feedforward feedback convenient low power design of accelerometer system structure, the establishment in the Matlab Simulink contains kT/C noise, noise amplifier, a behavioral model of the non ideal factors of the clock jitter, the obtained simulation results for SNDR:101.5dB, ENOB:16.57dits. power through the test chip analysis structure can be optimized for the circuit design. Discuss the design method of low power consumption, in the analog circuit noise, dynamic range and other restrictions on the power consumption, and low power consumption power consumption analysis and detailed design of the operational amplifier switch capacitor circuit. Based on the simulation theory and action on the 0.5 m based on the CMOS technique, the various functional modules to complete the design of.Sigma-Delta digital acceleration of five order low power digital accelerometer interface circuit Cadence interface circuit of the system can be Normal operation. The power supply voltage is 5V. The power consumption of the whole circuit is 9.4mW and the range is 2G. The noise level of the output signal is -140dBV/Hz1/2, sensitivity 320mV/g, equivalent input acceleration noise is 0.8 g/Hz1/2..

【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 吉訓(xùn)生,王壽榮;電容式硅微機(jī)械加速度計(jì)系統(tǒng)的特性研究[J];宇航學(xué)報(bào);2005年04期

，

本文編號：1533387