基于CNFET的高性能三值SRAM-PUF電路設(shè)計(jì)
本文關(guān)鍵詞: 碳納米管場(chǎng)效應(yīng)晶體管 三值邏輯 SRAM-PUF 隨機(jī)性 唯一性 出處:《電子學(xué)報(bào)》2017年05期 論文類型:期刊論文
【摘要】:通過對(duì)碳納米管場(chǎng)效應(yīng)晶體管(Carbon Nanotube Field Effect Transistor,CNFET)和物理不可克隆函(Physical Unclonable Functions,PUF)電路的研究,提出一種高性能三值SRAM-PUF電路結(jié)構(gòu).該電路結(jié)構(gòu)首先利用交叉耦合三值反相器產(chǎn)生隨機(jī)電流,并對(duì)其電流進(jìn)行失配分析;然后結(jié)合三值SRAM單元的電流競(jìng)爭(zhēng)得到隨機(jī)的、不可克隆的三值輸出信號(hào)"0"、"1"和"2".在32nm CNFET標(biāo)準(zhǔn)模型庫(kù)下,采用HSPICE對(duì)所設(shè)計(jì)的三值SRAM-PUF電路進(jìn)行Monte Carlo仿真,分析其隨機(jī)性、唯一性等性能.模擬結(jié)果表明所設(shè)計(jì)的三值SRAM-PUF電路歸一化隨機(jī)性偏差和唯一性偏差均為0.03%,且與傳統(tǒng)二值CMOS設(shè)計(jì)的PUF電路相比工作速度提高33%,激勵(lì)響應(yīng)對(duì)數(shù)量為原來的(1.5)n倍.
[Abstract]:Based on the study of carbon Nanotube Field Effect transistor-CNFETs and physical Unclonable functions PUFF circuits, a high performance ternary SRAM-PUF circuit structure is proposed, in which the cross-coupled ternary inverters are used to generate random currents. The mismatch analysis of its current is carried out, and the random, uncloned ternary output signals "0", "1" and "2" are obtained by combining the current competition of ternary SRAM cells. Under the 32nm CNFET standard model library, the designed ternary SRAM-PUF circuits are simulated with HSPICE for Monte Carlo simulation. Analyzing its randomness, The simulation results show that the normalized and unique deviations of the ternary SRAM-PUF circuits are both 0.03 and 0.03. Compared with the traditional binary CMOS circuits, the operating speed of the designed PUF circuits is increased by 33%, and the number of excitation responses is 1.5 n times higher than that of the traditional binary CMOS circuits.
【作者單位】: 寧波大學(xué)電路與系統(tǒng)研究所;
【基金】:國(guó)家自然科學(xué)基金(No.61474068,No.61234002) 浙江省公益性技術(shù)應(yīng)用研究計(jì)劃項(xiàng)目(No.2016C31078) 浙江省自然科學(xué)基金(No.LQ14F040001) 寧波市自然科學(xué)基金(No.2015A610107)
【分類號(hào)】:TN402
【相似文獻(xiàn)】
相關(guān)期刊論文 前9條
1 吳訓(xùn)威;陳偕雄;;三值比較運(yùn)算及其電路實(shí)現(xiàn)[J];科技通報(bào);1986年04期
2 吳浩敏,莊南,陳偕雄;蛻化三值邏輯及其應(yīng)用[J];杭州大學(xué)學(xué)報(bào)(自然科學(xué)版);1993年03期
3 李樹榮;對(duì)稱三進(jìn)制邏輯CMOS電路的試制[J];微電子學(xué);1988年04期
4 吳訓(xùn)威 ,莊南 ,胡國(guó)安;三值符合運(yùn)算及其TTL電路實(shí)現(xiàn)[J];杭州大學(xué)學(xué)報(bào)(自然科學(xué)版);1985年01期
5 袁玉仁;CMOS三值邏輯系統(tǒng)探討[J];南昌大學(xué)學(xué)報(bào)(理科版);1990年03期
6 陳偕雄,吳訓(xùn)威;對(duì)稱三值邏輯及對(duì)稱三值CMOS電路[J];計(jì)算機(jī)學(xué)報(bào);1991年05期
7 沈繼忠,吳訓(xùn)威;nMOS三值邏輯電路[J];杭州大學(xué)學(xué)報(bào)(自然科學(xué)版);1992年01期
8 鄭啟倫,黃貫光;多值DYL電路的邏輯設(shè)計(jì)[J];電子學(xué)報(bào);1982年03期
9 ;[J];;年期
,本文編號(hào):1495902
本文鏈接:http://sikaile.net/kejilunwen/dianzigongchenglunwen/1495902.html