本文關(guān)鍵詞： 鎖相環(huán) 低噪聲 RFID 亞采樣 死區(qū)　出處：《中國科學(xué)技術(shù)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著無線通信技術(shù)的飛速發(fā)展,移動終端設(shè)備的需求不斷增加,WiFi,Bluetooth,RFID等短距離無線通信協(xié)議被廣泛的開發(fā)利用。所有的通信系統(tǒng)都需要一個穩(wěn)定的時鐘,基于鎖相環(huán)(PLL)的頻率合成器是無線收發(fā)機中的重要組成部分,為系統(tǒng)提供本振信號。時鐘的精度影響著系統(tǒng)的整體性能,因此一個低噪聲的時鐘信號源是高性能無線收發(fā)機中必不可少的。本文的目標(biāo)是設(shè)計實現(xiàn)低噪聲的鎖相環(huán)。首先介紹了鎖相環(huán)及其各組成模塊的基本原理、電路結(jié)構(gòu)及非理想效應(yīng);隨后分析了環(huán)路帶寬和相位裕度對鎖相環(huán)穩(wěn)定性的影響;最后基于連續(xù)時間線性相位域模型,分析了其相位噪聲性能。本文設(shè)計了一款應(yīng)用于超高頻RFID閱讀器的鎖相環(huán)電路。鎖相環(huán)輸出頻率為840 MHz-960 MHz,符合國際工不同地區(qū)的超高頻RF1D協(xié)議標(biāo)準(zhǔn)�？紤]協(xié)議對鎖定時間和相位噪聲性能的要求,本文選取環(huán)路帶寬為40KHz。設(shè)計采用0.13 μm CMOS工藝,仿真結(jié)果顯示,壓控振蕩器輸出頻率為1.6 GHz-2.0 GHz,VCO在偏離載波頻率100 KHz處的相位噪聲為-112 dBc/Hz。鎖相環(huán)的鎖定時間為100μs,頻偏100 KHz和1 MHz處相位噪聲分別為-106 dBc/Hz和-128 dBc/Hz。本文設(shè)計了可以快速鎖定的低噪聲亞采樣鎖相環(huán)。在亞采樣鎖相環(huán)鎖定狀態(tài)下分頻器不參與環(huán)路工作,因此減少了分頻器所貢獻的噪聲。另外,由亞采樣鑒相器和亞采樣電荷泵所貢獻的噪聲不會被放大N2倍,從而極大程度地減小了鎖相環(huán)的帶內(nèi)噪聲。采用對稱式的采樣器可以改善由VCO負載不匹配引入的參考雜散。為了縮短亞采樣鎖相環(huán)的鎖定時間,本文提出了可調(diào)節(jié)死區(qū)閾值的鑒頻鑒相器,對其進行了理論分析,并與傳統(tǒng)固定死區(qū)閾值的鑒頻鑒相器進行了對比。設(shè)計采用0.18μm CMOS工藝,仿真結(jié)果顯示,鎖相環(huán)鎖定時間為3μs,參考雜散為-79.81 dBc。在偏移載波頻率200 KHz處,鎖相環(huán)帶內(nèi)噪聲為-124dBc/Hz。
[Abstract]:With the rapid development of wireless communication technology, the demand of mobile terminal equipment is increasing. Short-range wireless communication protocols such as RFID are widely used. All communication systems need a stable clock. The frequency synthesizer based on PLL (PLL) is an important part of wireless transceiver, which provides the local oscillator signal for the system. The precision of clock affects the overall performance of the system. Therefore, a low noise clock signal source is essential in high performance wireless transceiver. The goal of this paper is to design and implement low noise PLL. Firstly, the basic principle of PLL and its components are introduced. Circuit structure and non-ideal effect; Then the influence of loop bandwidth and phase margin on the stability of PLL is analyzed. Finally, it is based on continuous time linear phase domain model. The phase noise performance is analyzed. A PLL circuit for UHF RFID reader is designed. The output frequency of PLL is 840 MHz-960 MHz. Meet the UHF RF1D protocol standards in different parts of the international industry. Consider the requirements of the protocol for locking time and phase noise performance. In this paper, the loop bandwidth of 40kHz is chosen. The design adopts 0.13 渭 m CMOS process. The simulation results show that the output frequency of the VCO is 1.6 GHz-2.0 GHz. The phase noise of VCO is -112dBc / Hz. the locking time of PLL is 100 渭 s. The phase noise at 100 KHz and 1 MHz frequency offset is -106 dBc/Hz and -128, respectively. In this paper, we design a low-noise sub-sampling phase-locked loop which can be locked quickly. The frequency divider does not participate in the loop operation under the sub-sampling phase-locked state. Thus, the noise contributed by the frequency divider is reduced. In addition, the noise contributed by the subsampling phase discriminator and the subsampling charge pump is not amplified by N2 times. Therefore, the in-band noise of PLL is greatly reduced. The reference spurious introduced by VCO load mismatch can be improved by using symmetrical sampler. In order to shorten the locking time of sub-sampling PLL. In this paper, a phase discriminator with adjustable dead-zone threshold is proposed and analyzed theoretically, and compared with that of traditional fixed-dead-zone threshold. The design adopts 0.18 渭 m CMOS process. The simulation results show that the locking time of PLL is 3 渭 s and the reference spurious is -79.81 dBc. At the offset carrier frequency of 200 KHz, the in-band noise of PLL is -124dBc / Hz.
【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN386;TP391.44

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本文編號：1482232