本文關(guān)鍵詞： SRAM 工藝變化 低電壓 復(fù)制位線 靈敏放大器 時(shí)序偏差 失調(diào)電壓　出處：《安徽大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路(IC)行業(yè)快速發(fā)展,高集成度,高速低功耗已成為未來集成電路發(fā)展的趨勢(shì)。高集成度需要更小的半導(dǎo)體工藝尺寸,然而工藝尺寸較小會(huì)引起較大的工藝偏差。為了實(shí)現(xiàn)低功耗的目的,供電電壓也在不斷降低。然而電源電壓不斷降低加重了工藝偏差對(duì)電路的影響。SRAM作為IC中重要的組成部分,這種不斷增大的工藝偏差會(huì)對(duì)SRAM性能造成嚴(yán)重的影響,尤其對(duì)SRAM的工作速度,功耗以及穩(wěn)定性方面影響最為突出。針對(duì)這些工藝偏差帶來的問題,本文從復(fù)制位線以及靈敏放大器的的角度做了一些抗工藝變化的改進(jìn)。本文主要做的研究工作如下:首先分析了 SRAM基本框架結(jié)構(gòu)以及工作原理,然后分析了工藝偏差對(duì)SRAM里面時(shí)序信號(hào)以及靈敏放大器的影響,基于對(duì)兩者的分析,對(duì)已有的幾種常見的時(shí)序控制電路以及靈敏放大器做出分析,并且在SIMC 28nm工藝下對(duì)其結(jié)果進(jìn)行仿真和比較。針對(duì)工藝變化給SRAM電路帶來的負(fù)面影響,本文從復(fù)制位以及靈敏放大器兩個(gè)方面做了改進(jìn),首先提出了一種帶有觸發(fā)器的流水型復(fù)制位線技術(shù)用于減少工藝變化對(duì)時(shí)序信號(hào)的影響,然后又從靈敏放大器的角度提出了一種自反饋襯底調(diào)節(jié)的抗工藝變化的靈敏放大器電路用于減少工藝偏差對(duì)靈敏放大器失調(diào)電壓的影響。為了驗(yàn)證所提的改進(jìn)型電路的性能,我們對(duì)所提電路進(jìn)行蒙特卡洛仿真,與傳統(tǒng)的復(fù)制位線技術(shù)仿真結(jié)果相比,帶有觸發(fā)器的流水型復(fù)制位線技術(shù)抗工藝偏差減少了 81.34%。與傳統(tǒng)統(tǒng)的電壓型靈敏放大器仿真結(jié)果相比,帶有自反饋襯底調(diào)節(jié)的抗工藝變化的靈敏放大器的失調(diào)電壓減少了 31.73%。
[Abstract]:With the rapid development of IC industry, high integration, high speed and low power consumption have become the trend of IC development in the future. However, the smaller size of the process will cause a large process deviation, in order to achieve the purpose of low power consumption. The power supply voltage is also decreasing. However, the decrease of the supply voltage increases the influence of the process deviation on the circuit. SRAM is an important part of IC. This increasing process deviation will have a serious impact on the performance of SRAM, especially on the operating speed, power consumption and stability of SRAM. In this paper, some improvements are made from the point of view of replicating bit lines and sensitive amplifiers. The main research work of this paper is as follows: firstly, the basic frame structure and working principle of SRAM are analyzed. Then, the influence of process deviation on the timing signal and sensitive amplifier in SRAM is analyzed. Based on the analysis of both, several common timing control circuits and sensitive amplifiers are analyzed. The results are simulated and compared under the SIMC 28nm process. In view of the negative effects of the process changes on the SRAM circuits, this paper improves on the replication bit and the sensitive amplifier. Firstly, a income type replica bit line technique with trigger is proposed to reduce the influence of process change on timing signal. Then, from the point of view of sensitive amplifier, a kind of self-feedback substrate adjusted sensitive amplifier circuit is proposed to reduce the effect of process deviation on offset voltage of sensitive amplifier. Circuit performance. We do Monte Carlo simulation of the circuit and compare the simulation results with the traditional replica bit line technology. The income type replica bit line with flip-flop reduces the process deviation by 81.34. Compared with the simulation results of the traditional voltage-mode sensitive amplifier. The offset voltage of the sensitive amplifier with self-feedback substrate adjustment is reduced by 31. 73.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP333;TN722

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