本文關(guān)鍵詞： 數(shù)模轉(zhuǎn)換器 dual-ladder電阻分壓型結(jié)構(gòu) 自調(diào)整雙極性電壓源 噪聲 甲乙輸出級(jí)　出處：《湘潭大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：數(shù)模轉(zhuǎn)換器(digital-to-analog convertor,DAC)是連接在模擬IC與數(shù)字IC間的重要接口之一,是很多SOC芯片中不可或缺的一部分,本文設(shè)計(jì)的數(shù)模轉(zhuǎn)換器(DAC)是用于MEMS加速度計(jì)中,它是為了給系統(tǒng)提供一個(gè)穩(wěn)定的偏壓從而消除重力加速度對(duì)加速度計(jì)的影響,本課題是屬于國家十二五重大專項(xiàng),MEMS檢波器與地震數(shù)據(jù)采集系統(tǒng)關(guān)鍵技術(shù)的子項(xiàng)目。系統(tǒng)對(duì)DAC的要求包括:分辨率為12bit,電源電壓為±5V,差分參考電壓為+3.7V和-3.7V,微分非線性誤差(Differential non-linearity,DNL)小于0.25LSB,積分非線性誤差(Integral nonlinearity,INL)小于2LSB,且要求DAC的噪聲小于-120dBV?√。所設(shè)計(jì)的DAC采用的是dual-ladder電阻分壓型結(jié)構(gòu),其結(jié)構(gòu)特點(diǎn)為高6位粗分壓電阻陣列和低6位細(xì)分壓電阻陣列,這樣相比于普通的電阻串分壓型結(jié)構(gòu),可降低電阻匹配難度和版圖布局的難度。為避免傳統(tǒng)電壓源結(jié)構(gòu)所產(chǎn)生的電壓對(duì)稱性差和不精準(zhǔn)的問題,提出了自調(diào)整雙極性電壓源的結(jié)構(gòu)來產(chǎn)生3.7V和-3.7V的參考電壓,并且自調(diào)整電壓源中的反饋電阻即利用的電阻分壓陣列中的電阻,有效的減小了芯片面積。由于系統(tǒng)加速度計(jì)低噪聲的要求,詳細(xì)分析了DAC的輸出噪聲來源,并且從INL、噪聲以及功耗等方面進(jìn)行折中考慮,選取合適的DAC電阻陣列單位電阻值,并進(jìn)行兩次流片對(duì)比對(duì)噪聲進(jìn)行優(yōu)化。另外,由于DAC輸出端需要接一個(gè)160Ω的電阻和一個(gè)330μF的大電容,為使得輸出能在300ms內(nèi)達(dá)到穩(wěn)定,輸出緩沖器采用甲乙輸出級(jí)來減小輸出的穩(wěn)定時(shí)間。設(shè)計(jì)方法采用的是模擬集成電路設(shè)計(jì)的一般流程,根據(jù)指標(biāo)要求完成各個(gè)工藝角下的前后仿真,進(jìn)行了版圖設(shè)計(jì)、流片、測(cè)試等工作。此DAC在旺宏(MIXC)0.5um CMOS工藝中得以流片實(shí)現(xiàn),測(cè)試得到DAC的整體噪聲在3Hz時(shí)為-120dBV?√,而在15Hz時(shí)接近-140dBV?√,結(jié)果滿足系統(tǒng)指標(biāo)的要求,并且此DAC被成功的應(yīng)用到MEMS加速度計(jì)中。
[Abstract]:Digital-to-analog converter DAC is one of the important interfaces between analog IC and digital IC. It is an indispensable part of many SOC chips. The digital-to-analog converter designed in this paper is used in MEMS accelerometers. It is to provide a stable bias to the system so as to eliminate the impact of the acceleration of gravity on the accelerometer. MEMS geophone and seismic data acquisition system key technology subprojects. The system requirements for DAC include: resolution of 12 bits, power supply voltage of 鹵5V. The differential reference voltage is 3.7V and -3.7V, and the differential nonlinear error is less than 0.25LSB. The integral nonlinear error is less than 2LSBand the noise of DAC is less than -120dBV? The DAC is designed with a dual-ladder resistor split voltage structure, which is characterized by a high 6 bit coarse partial voltage resistor array and a low 6 bit subdivided voltage resistance array. Compared with the common resistance series voltage divider structure, it can reduce the difficulty of resistor matching and layout. In order to avoid the problem of voltage symmetry and inaccuracy caused by the traditional voltage source structure. The structure of self-adjusting bipolar voltage source is proposed to generate 3.7V and -3.7V reference voltage, and the feedback resistance in the self-adjusting voltage source is the resistance in the resistor partial voltage array. Because of the low noise requirement of the accelerometer, the source of output noise of DAC is analyzed in detail, and the compromise is made from the aspects of INL, noise and power consumption. Select the appropriate unit resistance of DAC resistor array and optimize the noise by comparing the two flowsheets. Because the DAC output needs a resistor of 160 惟 and a large capacitance of 330 渭 F, the output can be stabilized within 300ms. The output buffer adopts A / B output stage to reduce the stable time of output. The design method adopts the general flow of analog integrated circuit design and completes the simulation of each process angle according to the requirements of the index. Layout design, flow sheet, test and so on are carried out. This DAC can be realized in the CMOS process. The global noise of DAC is -120dBV? And close to -140 dBV at 15 Hz? The results meet the requirements of the system, and the DAC is successfully applied to the MEMS accelerometer.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

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相關(guān)期刊論文 前1條

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本文編號(hào)：1454461