FPGA物理不可克隆函數(shù)及其實現(xiàn)技術(shù)
發(fā)布時間:2018-01-21 04:53
本文關(guān)鍵詞: 物理不可克隆函數(shù) FPGA 硬件安全 出處:《計算機輔助設(shè)計與圖形學(xué)學(xué)報》2017年09期 論文類型:期刊論文
【摘要】:作為一種重要的硬件安全原語,物理不可克隆函數(shù)(PUF)利用集成電路不可控的制造工藝差異生成具有唯一標志的簽名數(shù)據(jù),以其特有的輕量級和防篡改屬性在芯片認證、隨機數(shù)產(chǎn)生器和密鑰生成等硬件安全領(lǐng)域具有極大優(yōu)勢.現(xiàn)場可編程門陣列(FPGA)應(yīng)用因其對電路設(shè)計可自由靈活配置的特點,自身的安全性和可靠性問題越來越受到關(guān)注.PUF技術(shù)可以從硬件層面為FPGA電路提供有效安全保護,以較少的開銷獲得更強的抵御安全風(fēng)險能力.文中系統(tǒng)地分析了基于FPGA PUF的模型和相應(yīng)的電路結(jié)構(gòu),總結(jié)和分析FPGA PUF電路結(jié)構(gòu)在隨機性、穩(wěn)定性和資源消耗等性能方面的優(yōu)化策略,FPGA PUF技術(shù)的主要檢驗評價方法以及性能對比;介紹了FPGA PUF在硬件安全領(lǐng)域中的典型應(yīng)用.最后對FPGA PUF面臨的挑戰(zhàn)和未來趨勢進行了展望.
[Abstract]:As an important hardware security primitive, the physical non-clone function PUFs generate unique signature data by using the uncontrollable manufacturing process difference of integrated circuits. With its unique lightweight and tamper-proof properties in the chip authentication. The application of FPGA (Field Programmable Gate Array) has great advantages in hardware security such as random number generator and key generation because of its flexible configuration for circuit design. More and more attention has been paid to the security and reliability of its own. PUF technology can provide effective security protection for FPGA circuits from the hardware level. The model based on FPGA PUF and the corresponding circuit structure are analyzed systematically. The optimization strategy of FPGA PUF circuit structure in randomness, stability and resource consumption is summarized and analyzed. The main test and evaluation methods and performance comparison of PUF technology are presented. This paper introduces the typical application of FPGA PUF in the field of hardware security. Finally, the challenges and future trends of FPGA PUF are prospected.
【作者單位】: 中國礦業(yè)大學(xué)(北京)機電與信息工程學(xué)院;清華大學(xué)計算機科學(xué)與技術(shù)系;
【基金】:國家自然科學(xué)基金(61176035)
【分類號】:TN791
【正文快照】: 聽、偽造和篡改等威脅.傳統(tǒng)的加密方法由于計算量大需要耗費更多資源,因此輕量級加密與認證技術(shù)的探索對于無線傳感器等資源受限物理設(shè)備具有重大意義.邏輯門電路是數(shù)字電路中的重要組成部分,由于集成電路制造工藝過程的特性,每一個邏輯門電路的閾值電壓以及氧化層厚度都不盡,
本文編號:1450527
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