本文關(guān)鍵詞：50Mbps低功耗時(shí)鐘數(shù)據(jù)恢復(fù)電路設(shè)計(jì)　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 時(shí)鐘數(shù)據(jù)恢復(fù)電路(CDR) 全速率雙環(huán)結(jié)構(gòu) 壓控振蕩器 抖動(dòng)(jitter) 襯底噪聲

【摘要】：串行傳輸技術(shù)僅采用數(shù)據(jù)線,節(jié)省了傳輸成本,降低了共享時(shí)鐘引起噪聲,是當(dāng)今信息傳輸?shù)闹饕绞�。時(shí)鐘數(shù)據(jù)恢復(fù)電路(CDR)是串行傳輸系統(tǒng)接收端的核心,其主要功能是提取嵌入到數(shù)據(jù)流中的時(shí)鐘信息,在該時(shí)鐘信號(hào)的幫助下進(jìn)行采樣,恢復(fù)傳輸?shù)臄?shù)據(jù),以消除數(shù)據(jù)在發(fā)送器、接收器間傳輸引入的抖動(dòng)。對(duì)于目前已經(jīng)量產(chǎn)化的單芯片以太網(wǎng)物理層收發(fā)器,百兆內(nèi)的傳輸速率以及靈活的電源管理架構(gòu),在保證傳輸速率的要求下,低功耗時(shí)鐘數(shù)據(jù)恢復(fù)是基本訴求。本文使用SMIC0.18μm CMOS工藝實(shí)現(xiàn)50Mbps低功耗時(shí)鐘數(shù)據(jù)恢復(fù)電路的設(shè)計(jì),采用基于鎖相環(huán)帶外部參考時(shí)鐘的全速率雙環(huán)結(jié)構(gòu)。為了提高穩(wěn)定性,環(huán)路選擇三階;為了實(shí)現(xiàn)低功耗,壓控振蕩器(VCO)采用單端五級(jí)環(huán)形結(jié)構(gòu);同時(shí)濾波器電容使用MOS管電容以節(jié)省版圖面積。使用Verilog-A并利用移位寄存器結(jié)合異或來實(shí)現(xiàn)輸入隨機(jī)NRZ序列的產(chǎn)生,以便對(duì)CDR進(jìn)行測(cè)試。CDR環(huán)路在74.6us完成鎖定,恢復(fù)的數(shù)據(jù)能夠正確跟隨輸入,且恢復(fù)的時(shí)鐘下降沿在輸入數(shù)據(jù)中間采樣,控制線上的紋波為1.54m V,系統(tǒng)恢復(fù)的時(shí)鐘上升沿峰值抖動(dòng)為183ps,恢復(fù)的數(shù)據(jù)峰值抖動(dòng)為189.6ps。版圖布局與繪制時(shí)提前考慮襯底噪聲的影響,通過各方面的權(quán)衡以彌補(bǔ)電路設(shè)計(jì)中的不足,主要措施如:提高匹配性、物理距離隔離以及保護(hù)環(huán)等。后仿環(huán)路鎖定時(shí)間為77.04us,控制線上抖動(dòng)小于1m V,時(shí)鐘的峰峰值抖動(dòng)約為44ps。同時(shí),隨著芯片集成度的提高,襯底噪聲已成為混合信號(hào)電路設(shè)計(jì)的難題。數(shù)字電路向襯底注入噪聲,并經(jīng)過襯底傳播損害敏感模擬電路性能,使得系統(tǒng)可靠性降低甚至失效。為了具體分析襯底噪聲對(duì)CDR性能的影響,通過襯底噪聲的耦合原理,建立了CDR襯底等效模型、噪聲源模型、N_well模型和電源/地線模型。將建立的模型應(yīng)用于CDR電路中,由仿真知襯底噪聲使壓控振蕩器的輸出頻率受到影響,系統(tǒng)鎖定時(shí)間延長(zhǎng),恢復(fù)的時(shí)鐘和數(shù)據(jù)峰值抖動(dòng)增加,環(huán)路穩(wěn)定性下降。為了有效地抑制襯底噪聲,在建立的CDR襯底模型中加入保護(hù)環(huán),測(cè)得環(huán)路鎖定時(shí)間由噪聲影響的80.82us縮減至74.3us,恢復(fù)的時(shí)鐘抖動(dòng)和數(shù)據(jù)抖動(dòng)明顯減小。
[Abstract]:The serial transmission technology only uses the data line, which saves the transmission cost and reduces the noise caused by the shared clock. Clock data recovery circuit (CDR) is the core of serial transmission system, and its main function is to extract the clock information embedded in the data stream. With the help of the clock signal, the transmitted data is sampled to recover the transmitted data to eliminate the jitter caused by the data transmission between the transmitter and the receiver.; for the single chip Ethernet physical layer transceiver which has been mass-produced at present. Within 100 megabytes of transmission rate and flexible power management structure, under the requirements of ensuring the transmission rate. Low power clock data recovery is the basic demand. In this paper, 50 Mbps low power clock data recovery circuit is designed using SMIC0.18 渭 m CMOS technology. A full rate double loop structure based on PLL with external reference clock is adopted. In order to improve the stability, the loop selects the third order. In order to achieve low power consumption, the VCO (Voltage controlled oscillator) adopts a single-ended five-stage ring structure. At the same time, the filter capacitor uses the MOS transistor capacitor to save the layout area, and uses the Verilog-A and the shift register to combine the XOR to realize the generation of the input random NRZ sequence. In order to test the CDR, the CDR loop is locked at 74.6us, the recovered data can follow the input correctly, and the recovered clock drop edge is sampled in the middle of the input data. The ripple on the control line is 1.54 MV, and the peak jitter of the rising edge of the system recovery clock is 183ps. The peak jitter of recovered data is 189.6 ps.The influence of substrate noise is considered ahead of time when layout layout and drawing are taken into account. The main measures such as improving matching ability can compensate for the deficiency in circuit design through various tradeoffs. Physical distance isolation and protection ring, etc. The locking time of the back loop is 77.04us. the jitter on the control line is less than 1m V, and the peak jitter of the clock is about 44ps. at the same time. With the improvement of chip integration, substrate noise has become a difficult problem in the design of mixed signal circuits. Digital circuits inject noise into the substrate and propagate through the substrate to damage the performance of sensitive analog circuits. In order to analyze the influence of substrate noise on CDR performance, the equivalent model and noise source model of CDR substrate are established by the coupling principle of substrate noise. The output frequency of the VCO is affected by the substrate noise and the locking time of the system is prolonged. The peak jitter of recovered clock and data increases and the loop stability decreases. In order to suppress the substrate noise effectively, the protection ring is added to the established CDR substrate model. The loop locking time was reduced from 80.82us to 74.3us. the recovered clock jitter and data jitter were reduced obviously.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN432

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 趙麗爽;應(yīng)用于超高速光纖通信系統(tǒng)中的CDR電路的研究與設(shè)計(jì)[D];華中科技大學(xué);2011年

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本文編號(hào)：1434718