發(fā)布時(shí)間：2018-01-16 06:13

  本文關(guān)鍵詞：內(nèi)建自測(cè)試march算法的優(yōu)化研究　出處：《安徽大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： 內(nèi)建自測(cè)試 SRAM 故障模型 March算法

【摘要】：時(shí)至今日,隨著超大規(guī)模電路和超深亞微米工藝等相關(guān)技術(shù)日趨成熟,與之而來(lái)的問(wèn)題愈發(fā)突出,存儲(chǔ)器良品率已無(wú)法滿(mǎn)足工業(yè)生產(chǎn)需要。目前芯片的測(cè)試成為制約芯片發(fā)展的一大瓶頸,由于半導(dǎo)體工藝提高測(cè)試難度成本增加,集成電路自動(dòng)測(cè)試機(jī)(Automatic Test Equipment)測(cè)試已無(wú)法滿(mǎn)足常規(guī)測(cè)試需求,為了解決測(cè)試問(wèn)題,關(guān)于芯片的內(nèi)建自測(cè)試BIST研究越來(lái)越深入。在片上系統(tǒng)(SOC)的微電子應(yīng)用中大容量嵌入式存儲(chǔ)器對(duì)內(nèi)建自測(cè)試的依賴(lài)愈加突出。由于嵌入式存儲(chǔ)器難以從芯片管腳訪(fǎng)問(wèn),從內(nèi)部測(cè)試恰好解決此問(wèn)題。對(duì)測(cè)試時(shí)所檢測(cè)到的故障模型盡可能大面積覆蓋,提高良品率促進(jìn)工業(yè)生產(chǎn)。所以,有效的故障模型,有效的測(cè)試算法及其實(shí)現(xiàn)是嵌入式存儲(chǔ)器內(nèi)建自測(cè)試設(shè)計(jì)的關(guān)鍵所在。本篇論文主要針對(duì)時(shí)下內(nèi)建自測(cè)試BIST和相關(guān)算法優(yōu)化的研究。本文首先介紹目前測(cè)試技術(shù)的發(fā)展,然后對(duì)靜態(tài)隨機(jī)存儲(chǔ)器SRAM、故障類(lèi)型進(jìn)行詳細(xì)說(shuō)明,隨后詳述了MBIST工作流程。最后重點(diǎn)闡述了March算法及其變種,詳細(xì)分析解讀了相關(guān)故障模型的原因和解決途徑。在目前常用算法March C-的基礎(chǔ)上提出自己的新算法March C-D,對(duì)March C-無(wú)法覆蓋的偽讀破壞故障DRDF進(jìn)行了良好的覆蓋,并詳細(xì)分析此算法針對(duì)相關(guān)故障進(jìn)行測(cè)試工作的過(guò)程,得到理論上的驗(yàn)證。最后基于Modelsim平臺(tái)進(jìn)行仿真驗(yàn)證March C-D算法的正確性和可行性。此改進(jìn)算法有更高的覆蓋率,并降低MarchC算法檢測(cè)故障時(shí)的重復(fù)率。對(duì)進(jìn)一步提高芯片的檢測(cè)的良品率有顯著效果。
[Abstract]:Today, with the development of ultra-large scale circuits and ultra-deep submicron technology, the problems become more and more serious. The memory quality rate can not meet the needs of industrial production. At present, chip testing has become a major bottleneck restricting the development of chips, because of the semiconductor process to increase the cost of difficult testing. IC automatic Test equipment testing can not meet the requirements of conventional testing, in order to solve the test problem. The research on built-in self-test BIST is getting deeper and deeper. System on Chip (SOC). Because embedded memory is difficult to access from chip pin, the dependence of embedded memory on built-in self-test is more and more prominent in microelectronic applications. From the internal test to solve this problem. The fault model detected during the test as much as possible coverage, improve the rate of good products to promote industrial production. Therefore, effective fault model. Effective test algorithm and its implementation are the key of embedded memory built-in self-test design. This paper mainly focuses on the research of built-in self-test BIST and the optimization of related algorithms. Firstly, this paper introduces the current test. The development of trial technology. Then the static random access memory (SRAM), the fault type is described in detail, and then the MBIST workflow is described. Finally, the March algorithm and its variants are described emphatically. The causes and solutions of the related fault models are analyzed in detail. On the basis of March C-, a new algorithm, March C-D, is proposed. The pseudo read failure DRDF which can not be covered by March C- is well covered, and the testing process of this algorithm for related faults is analyzed in detail. Finally, the correctness and feasibility of March C-D algorithm are verified by simulation based on Modelsim platform. This improved algorithm has higher coverage. It also reduces the repetition rate of MarchC algorithm for detecting faults, which has remarkable effect on further improving the rate of good products in chip detection.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN407

【參考文獻(xiàn)】

相關(guān)期刊論文 前3條

1 石磊;王小力;;一種基于存儲(chǔ)器故障原語(yǔ)的March測(cè)試算法研究[J];微電子學(xué);2009年02期

2 丁學(xué)君;田勇;;嵌入式存儲(chǔ)器的測(cè)試及可測(cè)性設(shè)計(jì)研究[J];世界電子元器件;2012年11期

3 宋毅;陽(yáng)輝;方葛豐;尹新;何怡剛;;嵌入式存儲(chǔ)器內(nèi)建自測(cè)試方法[J];微計(jì)算機(jī)信息;2008年31期

相關(guān)碩士學(xué)位論文 前1條

1 李少卿;視頻格式轉(zhuǎn)換芯片的可測(cè)性設(shè)計(jì)與形式驗(yàn)證[D];天津大學(xué);2011年

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本文編號(hào)：1431877