本文關(guān)鍵詞：適用于多通道生物信號(hào)采集系統(tǒng)的增量型Sigma-Delta ADC設(shè)計(jì)　出處：《浙江大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 多通道 信號(hào)采集 增量型Sigma-Delta ADC 調(diào)制器 數(shù)字抽取濾波器

【摘要】：當(dāng)前,植入式和便攜式生物醫(yī)療儀器已經(jīng)逐漸進(jìn)入了人們的視野,而多通道生物信號(hào)采集系統(tǒng)則是其中的核心模塊。為了滿足多個(gè)信號(hào)采集通道、高信號(hào)還原性能和微型化等設(shè)計(jì)要求,本文提出了適用于多通道生物系統(tǒng)采集系統(tǒng)的高精度低功耗增量型Sigma-Delta ADC。 設(shè)計(jì)方案主要包含增量型Sigma-Delta調(diào)制器及數(shù)字抽取濾波器的設(shè)計(jì)。與傳統(tǒng)Sigma-Delta調(diào)制器不同的是,增量型設(shè)計(jì)中需要考慮額外的復(fù)位信號(hào)和過采樣率等限制條件。綜合考慮系統(tǒng)需求和不同結(jié)構(gòu)的性能,本文采用了3階單比特量化CIFF結(jié)構(gòu)。在系統(tǒng)建模仿真中,為了更為接近實(shí)際情況,噪聲和積分器中運(yùn)放的非理想因素都被加入到理想模型之中。噪聲包含熱噪聲和閃爍噪聲兩部分,運(yùn)放中的非理想因素包括DC增益、增益帶寬積(Gain Bandwidth, GBW)和擺率(Slew-Rate, SR)等。 在電路實(shí)現(xiàn)設(shè)計(jì)中,采用了一級(jí)電流鏡結(jié)構(gòu)來實(shí)現(xiàn)積分器中的運(yùn)放,且其中采用電流消耗(Current Starvation)技術(shù)和電阻補(bǔ)償技術(shù)來提升運(yùn)放增益和帶寬等性能,使運(yùn)放能更為穩(wěn)定地工作。調(diào)制器中采用了斬波調(diào)制技術(shù)來抑制低頻閃爍噪聲。為解決低電源電壓所導(dǎo)致的開關(guān)非線性問題,采用了時(shí)鐘電壓提升技術(shù)。仿真表明在幅值為-12dB,頻率為4kHz的正弦波輸入下,調(diào)制器的信號(hào)噪聲失真比(Signal-to-Noise and Distortion Ratio, SNDR)達(dá)到了96.9dB,功耗和品質(zhì)因素(Figure of Merit, FOM)分別為40μW和435fJ/conversion-step。 此外,本文還完成了由級(jí)聯(lián)梳狀(Cascaded of Integrators Comb, CIC)濾波器和兩級(jí)半帶濾波器組成了數(shù)字抽取濾波器的設(shè)計(jì)。仿真結(jié)果表明,本文所設(shè)計(jì)的數(shù)字濾波器能夠完成降采樣和濾波器的功能,并且不影響調(diào)制器輸出信號(hào)的性能。
[Abstract]:At present, implantable and portable biomedical devices has gradually entered people's field of vision, and multi-channel biological signal acquisition system is one of the core modules. In order to meet the needs of multiple signal acquisition channels, high performance and miniaturization of signal design, is proposed in this paper is suitable for multi-channel biological systems acquisition system with high precision and low the power consumption increment Sigma-Delta ADC.
The design scheme includes incremental Sigma-Delta modulator and digital decimation filter. Different from the traditional Sigma-Delta modulator is considering additional reset signal and the oversampling rate restrictions require incremental design. Considering the system requirements and different structure performance, this paper adopts 3 order single bit quantization CIFF structure in the system. Modeling and simulation, in order to more close to the actual situation, the non ideal factors of noise and the op amp integrator were added to the ideal model. The noise consists of two parts of thermal noise and flicker noise, non ideal factors including DC operational amplifier gain, gain bandwidth product (Gain Bandwidth, GBW) and slew rate (Slew-Rate, SR).
In circuit design, using a current mirror structure to achieve the integrator amplifier, and the current consumption (Current Starvation) technology and resistance compensation technology to improve the amplifier gain and bandwidth performance, which can work stably for more operational amplifier. The modulator using chopper modulation technique to suppress the low frequency flicker noise. In order to solve the nonlinear problem caused by switching to low voltage, the clock voltage lift technique. The simulation shows that the amplitude of -12dB, frequency of sine wave input 4kHz, the signal to noise and distortion ratio (Signal-to-Noise and Distortion Ratio, SNDR) reached 96.9dB, and the power quality factor (Figure of, Merit, FOM) 40 W and 435fJ/conversion-step. respectively.
In addition, this paper also completed by the CIC (Cascaded of Integrators Comb, CIC) design consists of a digital decimation filter filter and two stage half band filter. The simulation results show that the digital filter is designed in this paper can complete the down sampling and filter function, and does not affect the performance of the modulator output signal.

【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN761;TN713

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本文編號(hào)：1431398