本文關(guān)鍵詞：基于verilog的小數(shù)分頻器的設(shè)計(jì)　出處：《北京工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 頻率綜合器 小數(shù)分頻器 Verilog FPGA

【摘要】：隨著集成電路的迅猛快速發(fā)展,頻率綜合器在電路中所起的作用顯得越來越重要。眾所周知,小數(shù)分頻器作為頻率綜合器的重要組成部分,其性能、功耗等指標(biāo)決定了一個(gè)頻率綜合器的頻率合成精度。具體來看,小數(shù)分頻器對于頻率綜合器的輸出精度,相位噪聲,鎖定時(shí)間等性能有重要影響。本文通過具體數(shù)據(jù)分析了當(dāng)前集成電路發(fā)展過程中數(shù)字電路所起的重要作用,并且著重介紹了頻率綜合器的研究現(xiàn)狀,說明了小數(shù)分頻器是當(dāng)今數(shù)字電路研究中一個(gè)重要研究方向。本文通過分析當(dāng)前小數(shù)分頻器研究領(lǐng)域中幾種主要的電路實(shí)現(xiàn)形式,發(fā)現(xiàn)尚未有利用純數(shù)字電路實(shí)現(xiàn)的小數(shù)分頻器。故本文在雙模前置小數(shù)分頻器的基礎(chǔ)上,提出了一種通過數(shù)字電路實(shí)現(xiàn)的可編程的小數(shù)分頻電路。本文提出了數(shù)字電路實(shí)現(xiàn)的可編程的小數(shù)分頻器的算法。分析了現(xiàn)有的小數(shù)分頻器的算法。提出了本小數(shù)分頻器的參數(shù)計(jì)算方法,即逐次逼近的參數(shù)計(jì)算方式。分析了誤差成因,設(shè)計(jì)了控制誤差的方法。通過實(shí)例展示了分頻參數(shù)的計(jì)算過程。本文設(shè)計(jì)實(shí)現(xiàn)了小數(shù)分頻器的參數(shù)計(jì)算模塊以及FPGA分頻模塊。其中包括浮點(diǎn)加法器、浮點(diǎn)乘法器、整數(shù)除法器等模塊。程序通過verilog語言實(shí)現(xiàn)。本文對設(shè)計(jì)的小數(shù)分頻器進(jìn)行了仿真及原型驗(yàn)證。包括小數(shù)分頻電路的參數(shù)計(jì)算單元與整體電路仿真,小數(shù)分頻器FPGA原型驗(yàn)證。仿真結(jié)果及邏輯分析儀測試結(jié)果均表明電路達(dá)到了設(shè)計(jì)要求。小數(shù)分頻器的誤差可以控制在以10E-9以內(nèi)。
[Abstract]:With the rapid development of integrated circuits, frequency synthesizer plays an increasingly important role in the circuit. As we all know, fractional frequency divider is an important part of frequency synthesizer. Power consumption and other indicators determine the frequency synthesis accuracy of a frequency synthesizer. Specifically, the frequency synthesizer output accuracy, phase noise of the fractional frequency synthesizer. This paper analyzes the important role of digital circuits in the development of integrated circuits through specific data, and emphatically introduces the research status of frequency synthesizers. It shows that fractional frequency divider is an important research direction in digital circuit research. This paper analyzes several main circuit realization forms in the field of fractional frequency divider research. It is found that there is no decimal frequency divider realized by pure digital circuit. A programmable fractional frequency divider realized by digital circuit is proposed in this paper. The algorithm of programmable fractional frequency divider realized by digital circuit is presented, and the existing algorithm of fractional frequency divider is analyzed. The parameter calculation method of the frequency divider. That is, the parameter calculation method of successive approximation. The cause of error is analyzed. The method of controlling error is designed, and the calculation process of frequency divider parameter is demonstrated by an example. The parameter calculation module of fractional frequency divider and the FPGA frequency division module are designed and implemented in this paper, including floating-point adder. Floating-point multiplier. Integer divider and other modules. The program is implemented by verilog language. The design of the fractional frequency divider is simulated and prototype verified, including the fractional frequency divider parameter calculation unit and the overall circuit simulation. FPGA prototype verification of fractional frequency divider. Simulation results and logic analyzer test results show that the circuit meets the design requirements. The error of fractional frequency divider can be controlled within 10E-9.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN772

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本文編號：1422588