本文關(guān)鍵詞：一種新型CMOS亞閾值四象限模擬乘法器的研究與設(shè)計(jì)　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 四象限模擬乘法器 低功耗 亞閾值 準(zhǔn)浮柵 襯底驅(qū)動(dòng) 電流模

【摘要】：隨著集成電路技術(shù)的高速發(fā)展,芯片的規(guī)模越來(lái)越大、處理能力越來(lái)越強(qiáng),功耗的問(wèn)題也越來(lái)越突出,特別是在便攜式電子設(shè)備上,由于電池的體積和重量不能做的太大,而續(xù)航時(shí)間卻要求更長(zhǎng),所以低功耗的電路設(shè)計(jì)成為現(xiàn)在集成電路設(shè)計(jì)的一個(gè)重要方向。不論是在便攜式電子設(shè)備中的通訊模塊中,還是在一些需要數(shù)學(xué)運(yùn)算的電路單元中,模擬成乘法器都是很重要的模塊。它經(jīng)常應(yīng)用于調(diào)制、解調(diào)、混頻、鑒相以及數(shù)學(xué)運(yùn)算單元中。因此設(shè)計(jì)功耗更小精度更高的模擬乘法器具有很重要的意義。本文設(shè)計(jì)了一個(gè)全新結(jié)構(gòu)的亞閾值四象限模擬乘法器,這種新結(jié)構(gòu)對(duì)乘法器的性能帶來(lái)很多好處。第一,不同于傳統(tǒng)的吉爾伯特型乘法器,它的核心結(jié)構(gòu)是由電流鏡構(gòu)成,通過(guò)襯底驅(qū)動(dòng)技術(shù)和電流鏡來(lái)實(shí)現(xiàn)乘法功能,同時(shí)襯底驅(qū)動(dòng)也增加了輸入的線性范圍;第二,通過(guò)向量矩陣相乘的結(jié)構(gòu)來(lái)實(shí)現(xiàn)差分四象限的乘法,這一結(jié)構(gòu)還便于對(duì)乘法器進(jìn)行擴(kuò)展;第三,通過(guò)與CMOS工藝兼容的準(zhǔn)浮柵技術(shù)來(lái)實(shí)現(xiàn)輸入信號(hào)的衰減以及和直流偏置電壓的疊加,這不僅增加輸入信號(hào)的線性范圍同時(shí)還能夠保證共模信號(hào)的穩(wěn)定;第四,該乘法器工作在亞閾值區(qū)域并且采用的是低電源電壓,所以功耗很低;第五,它的輸入輸出端口是電壓模式,便于集成在電路中,而它的乘法運(yùn)算卻是電流模式,所以又有著更快的速度。本文中亞閾值四象限模擬乘法器的電路設(shè)計(jì)采用的是0.18?m的TSMC工藝庫(kù),仿真工具是Cadence5.10.41。采用1V低電源電壓供電,由于工作在亞閾值區(qū)域,整個(gè)乘法器的總電流不大于100nA,因此功耗不大于0.1?W,由于采用了襯底驅(qū)動(dòng)以及準(zhǔn)浮柵技術(shù),該乘法器的輸入線性范圍可達(dá)300mV,輸入線性誤差小于3%,總諧波失真為1.05%,在偏置電流為30nA時(shí),乘法器的兩組輸入端中最差的-3dB帶寬也可達(dá)1.3MHz。該乘法器與吉爾伯特型的亞閾值模擬乘法器相比,有著帶寬更大、輸入線型范圍更大、電路規(guī)模更小、結(jié)構(gòu)擴(kuò)展更靈活的優(yōu)勢(shì),因此在低功耗模擬電路設(shè)計(jì)方面有著更大的潛力。
[Abstract]:With the rapid development of integrated circuit technology, the scale of the chip is becoming larger and larger, the processing power is more and more powerful, the problem of power consumption is more and more prominent, especially in the portable electronic equipment. Because of the size and weight of the battery can not be done too large, and the duration of the battery is required to be longer. Therefore, low power circuit design has become an important direction of integrated circuit design, whether in the communication module of portable electronic devices or in some circuit units that require mathematical operation. Analog multiplier is an important module. It is often used in modulation, demodulation and mixing. Therefore, it is very important to design analog multiplier with lower power consumption and higher precision. In this paper, a novel sub-threshold four-quadrant analog multiplier is designed. This new structure brings many benefits to the performance of the multiplier. First, unlike the traditional Gilbert multiplier, its core structure is composed of current mirrors. The multiplication function is realized by substrate driving technology and current mirror, and the linear range of input is increased by substrate driving. Secondly, the multiplication of the difference quadrant is realized by the structure of vector matrix multiplication, which is also convenient to extend the multiplier. Thirdly, the quasi-floating gate technology compatible with CMOS process is used to realize the attenuation of input signal and the superposition of DC bias voltage. This not only increases the linear range of input signal, but also ensures the stability of common-mode signal. 4th, the multiplier operates in the sub-threshold region and uses a low power supply voltage, so the power consumption is very low; 5th, its input and output port is voltage mode, easy to integrate in the circuit, and its multiplication is current mode. So there is a faster speed. In this paper, the circuit design of the sub-threshold four-quadrant analog multiplier is 0.18? M's TSMC process library, the simulation tool is Cadence 5.10.41. 1V low power supply voltage is used, because it works in the sub-threshold region. The total current of the whole multiplier is not greater than 100 na, so the power consumption is not greater than 0.1? Due to the use of substrate drive and quasi-floating gate technology, the input linearity range of the multiplier can reach 300mV, the input linearity error is less than 3 and the total harmonic distortion is 1.05%. When the bias current is 30nA, the worst -3dB bandwidth of the two groups of inputs of the multiplier can also reach 1.3 MHz. The multiplier has a larger bandwidth than the Gilbert subthreshold analog multiplier. Because of the advantages of larger input line, smaller circuit size and more flexible structure expansion, it has more potential in low power analog circuit design.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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