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  本文關(guān)鍵詞：基于CNFET的三值組合電路研究　出處：《寧波大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 多值邏輯 CNFET 低功耗 組合電路

【摘要】：二值信號(0,1)在集成電路領(lǐng)域應(yīng)用較多,但由于它攜帶的信息量少,導(dǎo)致電路的布線面積增加。為減小電路的布線面積和增加其對數(shù)據(jù)的處理能力,多值邏輯技術(shù)是一種有效方法。多值邏輯電路中每條布線攜帶的信息量大,輸入輸出引線數(shù)目少,單線攜帶信息的能力和集成電路的信息密度較高,因此它不僅提高電路空間和時間的利用率,還降低集成電路的生產(chǎn)成本。但是,目前的多值組合邏輯電路大多采用以CMOS工藝為基礎(chǔ)的場效應(yīng)晶體管,所設(shè)計出來的組合電路,其結(jié)構(gòu)的復(fù)雜性,能量的消耗都大幅度增加,故探討多值邏輯的低功耗組合電路設(shè)計顯得尤為重要。因此,通過對碳納米場效應(yīng)晶體管(CNFET)和多值邏輯組合電路的研究,以三值邏輯為代表,以組合邏輯電路為研究目標,提出一種基于CNFET的三值組合邏輯電路設(shè)計,該設(shè)計中利用CNFET新型器件的良好特性,降低了電路功耗,三值組合邏輯電路使電路的信息攜帶能力得到提高,從而為設(shè)計具有高信息密度與低功耗的組合邏輯電路提供了條件。論文將從以下幾個部分進行敘述:1、開關(guān)—信號理論和三值門電路和文字運算電路設(shè)計:深入研究開關(guān)—信號理論和CNFET的結(jié)構(gòu)特點,并根據(jù)此理論和特點設(shè)計基于CNFET的三值門電路和文字運算電路,為設(shè)計后續(xù)基于CNFET的三值組合邏輯電路奠定基礎(chǔ)。2、基于CNFET的三值編譯碼器設(shè)計:分析原有的三值編譯碼器原理和CNFET的結(jié)構(gòu)特性,以多值邏輯組合電路為基礎(chǔ),結(jié)合開關(guān)信號理論和文字運算電路的特點,設(shè)計基于CNFET的三值編譯碼器:1T-2B編譯碼、2T-3B編譯碼器。3、基于CNFET的多位三值比較器設(shè)計:分析三值比較器工作原理,根據(jù)多值邏輯電路的設(shè)計思想,設(shè)計帶有編譯碼器的兩位三值比較器,并結(jié)合多位比較原理設(shè)計基于CNFET的多位三值比較器。4、基于CNFET的三值逐次比較型模數(shù)轉(zhuǎn)換器(ADC)設(shè)計:分析三值逐次比較器的工作原理,引入三值電容陣列和多束編譯碼器電路,設(shè)計具有三值采樣與輸出的多值邏輯電路,最終實現(xiàn)基于CNFET的三值逐次比較型ADC。對上述所設(shè)計的組合電路進行HSPICE模擬分析,驗證所有組合電路的邏輯功能,然后與不同設(shè)計方法的組合電路進行功耗和速度比較,驗證其電路的高速低功耗特性。
[Abstract]:Two valued signal (0,1) is widely applied in the field of integrated circuits, but because of the amount of information it carries less lead wiring area increased. As the circuit wiring area reduction circuit and increase the data processing ability, multi valued logic technology is an effective method. The multi value information carried by the amount of each wiring logic circuit in large, input and output leads the number of small, high density single information information carrying capacity and the integrated circuit, so it can not only improve the circuit ratio of space and time, but also reduce the production cost of an integrated circuit. However, the current multi valued combinational logic circuit mostly adopts the field effect transistor is based on the CMOS process, combination the circuit is designed, the complexity of its structure, the energy consumption is greatly increased, so the design of low power combination circuit of multiple valued logic is very important. Therefore, based on the carbon nanotube field effect Transistor (CNFET) and study the multi valued logic combination circuit, three valued logic is represented, with a combinational logic circuit as the research object, this paper puts forward a design value of three combinational logic circuit based on CNFET, using the good properties of CNFET in the design of new devices, reduce power consumption, the three value of combinational logic circuit circuit information carrying capacity can be improved, so as to provide the conditions of combinational logic circuit with high information density and low power design. The thesis will be from the following parts: 1, the switch signal theory and the three value gate circuit and text arithmetic circuit design: structural features in-depth study of the switch signal theory and CNFET. And according to the theory and characteristics of the design of CNFET three value gate circuit and operational circuit based on the text, for the subsequent design based on CNFET three combinational logic circuits to lay the foundation for.2, CNFET three compiler based on value Decoder design: analysis of the structure characteristics of CNFET codec principle and the original value of three, with the combination of multiple valued logic circuits based on switch signal theory, combining the characteristics of text and arithmetic circuit, design of CNFET codec based on three values: 1T-2B codec, 2T-3B codec.3, CNFET value of more than three based on the analysis of three values: comparator design principle of comparator, according to multiple valued logic circuit design, the design of a two bit codec three value comparator, and combined with a number of more than three comparison principle CNFET design value comparator based on.4, based on the CNFET value of three successive type analog-to-digital converter (ADC) design: three the working principle of successive values of the comparator, the introduction of the three capacitor array and multi beam decoder circuit design with three sampling value and the output of the multiple valued logic circuit, finally realizes the CNFET value by three times compared to ADC. based on The design of the combinational circuit is simulated by HSPICE, and the logic functions of all combinational circuits are verified. Then, the power and speed of the combinational circuits with different design methods are compared to verify the high speed and low power consumption of the circuit.

【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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本文編號：1413250