本文關(guān)鍵詞：40nm工藝代中道寄生效應(yīng)及模型研究　出處：《華東師范大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 納米工藝代 柵圍寄生電容 模型擬合及參數(shù)提取 工藝波動(dòng) 參數(shù)化單元

【摘要】：隨著工藝節(jié)點(diǎn)不斷降低,版圖參數(shù)與器件結(jié)構(gòu)參數(shù)減小引起的版圖鄰近效應(yīng)及寄生效應(yīng)日趨顯著,同時(shí),工藝波動(dòng)對(duì)器件的影響也愈發(fā)不可忽略。因此,如何建立一個(gè)精確的MOSFET器件模型,使之能夠準(zhǔn)確描述上述版圖與器件結(jié)構(gòu)減小引起的寄生效應(yīng),有利于提高納米電路設(shè)計(jì)仿真的精確度�；谄骷Ｐ偷腜DK(Process Design Kit,工藝設(shè)計(jì)包),集全定制電路和半導(dǎo)體工藝于一體,可與模擬軟件和驗(yàn)證軟件搭載形成一個(gè)完整的設(shè)計(jì)平臺(tái),有利于降低設(shè)計(jì)成本。本文首先分析了 40nm MOSFET寄生電容組成部分,明確各寄生電容的電場(chǎng)線起止范圍,歸納各電容所屬類別。研究深納米下的隨機(jī)摻雜波動(dòng)、線邊緣粗糙度引起的關(guān)鍵尺寸等線寬波動(dòng)、柵氧等效厚度波動(dòng),介紹了光學(xué)鄰近效應(yīng)的影響及解決方案。在雙介質(zhì)垂直板電容基礎(chǔ)上,結(jié)合線邊緣粗糙度、等效柵氧化層、過(guò)刻蝕等工藝波動(dòng)及器件剖面的TEM圖,考慮了版圖布局參數(shù)CCS(接觸孔至接觸孔距離)、CPS(柵至接觸孔距離)對(duì)寄生效應(yīng)的影響,建立了一個(gè)具有版圖相關(guān)性的半解析柵至源/漏邊緣電容模型。該電容模型與實(shí)測(cè)數(shù)據(jù)擬合度在±15%以內(nèi),在產(chǎn)業(yè)要求的誤差范圍內(nèi),可用于補(bǔ)充改善40nmMOSFET器件模型。寄生效應(yīng)不僅可以通過(guò)模型體現(xiàn),也可以通過(guò)PDK體現(xiàn)。本文基于Virtuoso平臺(tái),介紹了 PDK流程以及器件描述格式在電路設(shè)計(jì)中的作用。按照模型參數(shù)要求,對(duì)40nm射頻器件進(jìn)行SKILL語(yǔ)言的編寫,通過(guò)回調(diào)函數(shù)實(shí)現(xiàn)了對(duì)器件基本物理結(jié)構(gòu)以及阱鄰近效應(yīng)等寄生效應(yīng)的處理,實(shí)現(xiàn)了 MOS晶體管以及傳輸線等器件的參數(shù)化單元設(shè)計(jì)。本文基于40nm工藝研究平臺(tái),提取了 MOS器件的版圖相關(guān)性的柵極電容,實(shí)現(xiàn)了射頻器件的參數(shù)化單元,為進(jìn)一步深入發(fā)展40nm工藝提供了研究?jī)r(jià)值。
[Abstract]:As the technology node decreases, the layout parameters and structural parameters of the device layout reduce proximity effect and parasitic effects caused by the increasingly prominent, at the same time, effects of process variations on devices become more and more can not be ignored. Therefore, how to set up an accurate MOSFET model, which can accurately describe the effect caused by the reduced parasitic layout and device the structure, is conducive to improve the simulation accuracy of nanometer circuit design. The device model based on PDK (Process Design Kit, the process design package), integrates the full custom circuit and semiconductor process, and simulation software and software verification with form a complete design platform, to reduce the cost of design. This paper first analyzes the 40nm MOSFET parasitic capacitance part, clear lines of the parasitic capacitance of the electric field range, including the capacitance category. The deep research of nano random dopant fluctuation, Line edge roughness caused by the key dimensions of linewidth fluctuation, equivalent gate oxide thickness fluctuation, the effect of optical proximity effect and solutions. In the double medium vertical plate capacitor based on the combination of line edge roughness, the equivalent gate oxide layer over etching device and process fluctuation profile TEM, considering the layout parameters CCS (distance contact hole to the contact hole (CPS), distance from the gate to the contact hole) influence on the parasitic effect, set up a model with the edge capacitance leakage layout correlation semi analytical gate to source /. The capacitance model and the measured data fitting degree is less than 15%, the error range of industry requirements in the improved 40nmMOSFET model can be used to supplement the parasitic effects. Through the model can not only reflect, but also by the PDK expression. This paper based on Virtuoso platform and introduces the PDK process and device description format in circuit design. In accordance with the requirements. The parameters of the model, to write SKILL language on the 40nm RF devices, through the callback function to deal with the basic physical structure of the device and the trap effect adjacent parasitic effect, realize the parametric design of unit MOS transistor and transmission line devices. This paper is based on the 40nm technology research platform, from the gate the capacitance of the MOS device layout correlation, realize the parametric unit RF devices, and provides the research value for the further development of 40nm technology.

【學(xué)位授予單位】：華東師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386

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本文編號(hào)：1408771