本文關(guān)鍵詞：X波段低相噪取樣DRO的研究　出處：《電子科技大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 取樣鎖相 介質(zhì)振蕩器 擴(kuò)捕電路 穩(wěn)定判決

【摘要】：為了滿足航天探測(cè)領(lǐng)域快速發(fā)展的要求,軍用微波系統(tǒng)的研制工作開始受到很多學(xué)者的關(guān)注。與此相關(guān)的技術(shù)很多,其中低相位噪聲的取樣鎖相頻率源集合了鎖相環(huán)路(PLL)和介質(zhì)振蕩器(DRO)兩者之長,被廣泛應(yīng)用于空間探測(cè)、測(cè)量儀器等特定領(lǐng)域。目前大多數(shù)生產(chǎn)的鎖相介質(zhì)振蕩器(PLDRO)多是依靠工程人員的實(shí)踐經(jīng)驗(yàn)完成設(shè)計(jì)與調(diào)試的,缺乏理論上的深度分析和指導(dǎo)。設(shè)計(jì)上也存在周期長、難度大等實(shí)際問題�；谝陨犀F(xiàn)狀,為了滿足型號(hào)任務(wù)需求,本題目主要目的是對(duì)X波段取樣鎖相介質(zhì)振蕩器進(jìn)行研制與實(shí)現(xiàn),旨在對(duì)取樣鑒相、擴(kuò)捕電路、穩(wěn)定判決等難點(diǎn)問題進(jìn)行深入的理論分析。本文通過ADS軟件仿真使介質(zhì)振蕩器電路的設(shè)計(jì)過程簡化,最終滿足型號(hào)指標(biāo)需要并對(duì)以后的設(shè)計(jì)工作起到參考作用。本文主要研究設(shè)計(jì)了一種9.66GHz的取樣PLDRO。在研究過程中,首先闡述了鎖相環(huán)的理論和結(jié)構(gòu)。在環(huán)路線性模型的基礎(chǔ)上著重分析了相位噪聲與穩(wěn)定性判決,并對(duì)環(huán)路的鎖定與失鎖問題進(jìn)行了介紹。然后對(duì)介質(zhì)振蕩器進(jìn)行理論分析與軟件仿真。在設(shè)計(jì)過程中,先通過電路仿真軟件ADS確定直流偏置參數(shù),然后建立了相應(yīng)的模型并做了模擬調(diào)試工作;再利用奈奎斯特穩(wěn)定性判決進(jìn)行起振仿真;然后得到相位噪聲、諧振頻率等仿真結(jié)果。最終在取樣鎖相電路的設(shè)計(jì)中,計(jì)算出環(huán)路參數(shù),并選取取樣鑒相芯片MSPD2018-H50實(shí)現(xiàn)取樣鎖相環(huán)路功能。為了確保此種電路可以長時(shí)間可靠工作,還同時(shí)選取了運(yùn)算放大器OP470設(shè)計(jì)了擴(kuò)捕掃描電路并對(duì)其進(jìn)行了輸出信號(hào)仿真。9.66GHz的PLDRO最終功率輸出為4.5dBm,在偏離載波1kHz、10kHz、100kHz以及1MHz處的相位噪聲分別是-93.5dBc/Hz@1kHz;-97.4dBc/Hz@10kHz;-100.1dBc/Hz@100kHz;-129.5dBc/Hz@1MHz,諧波抑制達(dá)到了-59.8dBc@2f0,達(dá)到了要求的設(shè)計(jì)目標(biāo)。
[Abstract]:In order to meet the rapid development of space exploration areas, development of military microwave system has been the concern of many scholars. The related technology, including sampling phase-locked frequency source with low phase noise collection phase locked loop (PLL) and dielectric resonator oscillator (DRO) of both, is widely used in space exploration and measurement the instrument and other specific areas. At present most of the production of the phase locked dielectric resonator oscillator (PLDRO) is completed by the experience of design and debugging, the lack of in-depth analysis and theoretical guidance. The design also exists in the long period, difficult practical problems. Based on the above situation, in order to meet the needs of the task type, title is the main purpose of the X band phase locked dielectric resonator oscillator was developed and implemented, aimed at the sampling phase, acquisition circuit, analyze the deep theory. The difficult problems such as stability judgment This paper makes the design process of dielectric resonator oscillator circuit is simplified by ADS simulation software, and ultimately meet the needs and model index reference for future design. This paper mainly studies the design of a 9.66GHz PLDRO. sample in the course of the study, first elaborated the PLL theory and structure. Based on the linear model of the loop focuses on the analysis of the phase noise and the stability of the judgment, and loop locked and unlocked problems were introduced. Then the theoretical analysis and Simulation of dielectric resonator oscillator. In the design process, first DC bias parameters were determined by the simulation software of ADS, and then established the corresponding model and make the simulation debugging work; reuse Nyquist stability judgment vibration simulation; and then obtain the phase noise, etc. the simulation results of the resonant frequency. Finally in the design of sampling phase locked circuit, calculate the ring road The parameters, and select the sampling phase detector chip MSPD2018-H50 to realize the PLL function. In order to ensure that the circuit can work reliably for a long time, also selected the OP470 operational amplifier designed to capture scanning circuit and the output signal simulation of.9.66GHz PLDRO to its final power output of 4.5dBm, 10kHz in 1kHz from the carrier, phase. 100kHz and 1MHz noise are -93.5dBc/Hz@1kHz; -97.4dBc/Hz@10kHz; -100.1dBc/Hz@100kHz; -129.5dBc/Hz@1MHz, harmonic suppression reached -59.8dBc@2f0, meet the design requirements.

【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN752

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本文編號(hào)：1378729