本文關(guān)鍵詞：功率STI-LDMOS器件熱載流子退化機(jī)理與壽命模型研究　出處：《東南大學(xué)》2016年碩士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： 熱載流子 淺槽隔離 LDMOS 壽命模型 可靠性

【摘要】：淺槽隔離(STI)工藝因其無(wú)鳥(niǎo)嘴、集成度高及隔離能力強(qiáng)等優(yōu)點(diǎn)成為深亞微米功率集成電路領(lǐng)域的主流,功率STI-LDMOS器件也因此成為應(yīng)用最廣的小尺寸功率器件。然而器件尺寸縮小并未帶來(lái)工作電壓的等比例縮小,熱載流子效應(yīng)導(dǎo)致的器件退化進(jìn)一步加劇,傳統(tǒng)功率LDMOS器件熱載流子效應(yīng)的研究結(jié)論已不能適用于功率STI-LDMOS器件。因此有必要對(duì)其新的退化機(jī)理及相關(guān)壽命模型展開(kāi)深入研究。本文首先利用I/V退化測(cè)試系統(tǒng)和Sentaurus TCAD仿真平臺(tái)研究并揭示了功率STI-LDMOS器件的退化機(jī)理：中柵壓高漏壓條件下器件退化由靠近源極的STI拐角處的界面態(tài)主導(dǎo),而高柵壓高漏壓條件下器件退化由靠近漏極的STI拐角處的界面態(tài)主導(dǎo)。另外,研究發(fā)現(xiàn)溫度越高,器件線性區(qū)漏極電流Idlin的退化越大,這是因?yàn)闇囟壬呓档土似骷拈撝惦妷?從而增大了電流,提高了器件內(nèi)部的碰撞電離率,加劇了器件退化。隨后,探討了器件壽命的考核方法,包括最壞應(yīng)力條件的選取和器件性能參數(shù)的監(jiān)測(cè)方法,進(jìn)而根據(jù)退化機(jī)理和考核標(biāo)準(zhǔn)建立了器件電學(xué)參數(shù)的退化壽命模型,通過(guò)驗(yàn)證發(fā)現(xiàn)模型的誤差在10%以內(nèi)。最后,基于上述退化機(jī)理和壽命模型對(duì)器件進(jìn)行了優(yōu)化,研究發(fā)現(xiàn)：增大溝道長(zhǎng)度、增大柵極場(chǎng)板長(zhǎng)度,減小STI側(cè)壁的傾斜角或增大STI拐角的曲率半徑均可提升器件的熱載流子可靠性。同時(shí),還提出了槽柵結(jié)構(gòu)、P型埋層結(jié)構(gòu)與分離柵結(jié)構(gòu)等三種具有高熱載流子可靠性的新型功率STI-LDMOS器件結(jié)構(gòu)。本文的成果對(duì)深亞微米功率器件的熱載流子效應(yīng)研究以及高可靠性器件設(shè)計(jì)具有借鑒意義。
[Abstract]:Shallow trench isolation (STI) technology because of its advantages of no bill, high integration and isolation ability has become the mainstream of deep submicron integrated circuit power field, power STI-LDMOS device has become a small size power device is the most widely used. However, the size reduction of the device does not bring the equal voltage reduction of the working voltage. The degradation of the device caused by the hot carrier effect is further intensified. The conclusion of the hot carrier effect of the conventional power LDMOS device is no longer applicable to power STI-LDMOS devices. Therefore, it is necessary to carry out a thorough study of its new degradation mechanism and related life model. This paper use the I/V degradation test research system and Sentaurus TCAD simulation platform and degradation mechanism of power STI-LDMOS devices that the gate voltage in high leakage pressure conditions by device degradation near the source STI interface state at the corner of the leading, and the high voltage interface state high leakage pressure conditions back from near the drain STI device at the corner of the leading. In addition, it is found that the higher the temperature is, the greater the degradation of Idlin is. The higher the temperature is, the lower the threshold voltage of the device, which will increase the current, increase the internal ionization rate and intensify the device degradation. Then, discusses the evaluation method of life of the device, the monitoring method including the selection of the worst stress conditions and device performance parameters, and then according to the electrical parameters of the device degradation life model established degradation mechanism and assessment standards, through verification model of the error is less than 10%. Finally, based on the above degradation mechanism and life model, the device is optimized. It is found that increasing the channel length, increasing the gate field length, reducing the inclination angle of the STI sidewall or increasing the radius of curvature of the STI corner can enhance the hot carrier reliability of the device. At the same time, three new power STI-LDMOS devices with high thermal carrier reliability are proposed, such as slot structure, P type buried layer structure and separation grid structure. The results of this paper are useful for the research of the hot carrier effect of deep submicron power devices and the design of high reliability devices.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN386

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本文編號(hào)：1340453