快速DVS響應(yīng)的降壓變換器設(shè)計(jì)
發(fā)布時(shí)間：2018-07-15 08:21
【摘要】：手持設(shè)備的快速發(fā)展對(duì)芯片的性能和功耗同時(shí)提出了更高要求。動(dòng)態(tài)電壓調(diào)節(jié)(Dynamic Voltage Scaling,DVS)正是其中一種普遍的解決方案[1]。但是有效的動(dòng)態(tài)電壓調(diào)節(jié)要求供電電壓的變化速度足夠快。LDO結(jié)構(gòu)相對(duì)簡(jiǎn)單,響應(yīng)速度也可以做到很快,但是存在輸出動(dòng)態(tài)范圍小和效率低的問(wèn)題。開關(guān)電源為此成為了首選,但如何做到快的DVS響應(yīng)一直是開關(guān)電源很大的問(wèn)題。為此,本文提出了電壓�？刂频木哂锌焖貲VS響應(yīng)的降壓變換器的設(shè)計(jì)方法,并設(shè)計(jì)和優(yōu)化了一款具有5MHz開關(guān)頻率的電壓模控制的降壓變換器。在設(shè)計(jì)方法上,本文重點(diǎn)分析了三型補(bǔ)償中,零極點(diǎn)位置對(duì)環(huán)路穩(wěn)定性的影響,并給出了設(shè)計(jì)實(shí)例。另外還定性地分析了降壓變換器中的復(fù)極點(diǎn)、占空比飽和、電感電流飽和以及偽三型補(bǔ)償?shù)慕Y(jié)構(gòu)對(duì)DVS響應(yīng)造成的影響。在電路設(shè)計(jì)上,本文給出了兩款芯片設(shè)計(jì)方案。兩款芯片采用了不同的偽三型補(bǔ)償方案,其中一款芯片是對(duì)另外一款芯片的優(yōu)化,并獲得性能上的提升。第一款降壓變換器芯片的設(shè)計(jì)基于0.13μm標(biāo)準(zhǔn)CMOS工藝。該降壓變換器的輸入電壓范圍為2.8V-3.6V,輸出電壓范圍為1.2V-1.8V,最大負(fù)載電流1A。測(cè)試結(jié)果顯示,發(fā)生DVS響應(yīng)時(shí),它的向上跟蹤速度為8.3μs/V,向下跟蹤速度為15μs/V。第二款降壓變換器芯片的設(shè)計(jì)基于40nm標(biāo)準(zhǔn)CMOS工藝。該降壓變換器的輸入電壓范圍為2.8V-3.6V,輸出電壓范圍為1V-2V,最大負(fù)載電流為1A。仿真結(jié)果顯示,發(fā)生DVS響應(yīng)時(shí),它的向上跟蹤速度為3.7μs/V,向下跟蹤速度為9.3μs/V。第二款芯片采用了新的偽三型補(bǔ)償拓?fù)?并采用非線性的方法有效抑制了下階躍響應(yīng)中可能引起的電壓下沖。兩款芯片都采用5MHz的開關(guān)頻率,4.7μF的輸出電容和1.1μH的電感。最終,該芯片驗(yàn)證了本文提出的具有快速DVS響應(yīng)的降壓變換器的設(shè)計(jì)方法。
[Abstract]:The rapid development of handheld devices requires higher performance and power consumption. Dynamic Voltage scaling (DVS) is one of the most popular solutions. However, effective dynamic voltage regulation requires that the power supply voltage change speed is fast enough. LDO structure is relatively simple, and the response speed can be achieved quickly, but there are some problems such as small dynamic range of output and low efficiency. Switching power supply has become the first choice for this, but how to achieve fast DVS response has been a big problem of switching power supply. For this reason, this paper presents the design method of a voltage-mode controlled step-down converter with fast DVS response, and designs and optimizes a voltage-mode controlled step-down converter with 5MHz switching frequency. In terms of design method, the influence of zero pole position on loop stability in three types compensation is analyzed, and a design example is given. In addition, the effects of complex poles, duty cycle saturation, inductance current saturation and pseudo-three-type compensation structure on DVS response are analyzed qualitatively. In the circuit design, this paper gives two chip design schemes. The two chips adopt different pseudo-three compensation schemes. One chip is optimized for the other chip and the performance is improved. The design of the first step-down converter is based on 0.13 渭 m standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1.2V-1.8V, and the maximum load current is 1A. The test results show that the upward tracking speed is 8.3 渭 s / V and the downward tracking speed is 15 渭 s / V when the DVS response occurs. The design of the second step-down converter is based on 40nm standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1V-2V, and the maximum load current is 1A. The simulation results show that the upward tracking speed is 3.7 渭 s / V and the downward tracking speed is 9.3 渭 s / V when DVS response occurs. The second chip adopts a new pseudo-three-type compensation topology, and the nonlinear method is used to effectively suppress the voltage downrush caused by the lower step response. Both chips use output capacitance of 4.7 渭 F and inductance of 1.1 渭 H with a switching frequency of 5 MHz. Finally, the chip verifies the proposed design method of the step-down converter with fast DVS response.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TM46
本文編號(hào)：2123449
[Abstract]:The rapid development of handheld devices requires higher performance and power consumption. Dynamic Voltage scaling (DVS) is one of the most popular solutions. However, effective dynamic voltage regulation requires that the power supply voltage change speed is fast enough. LDO structure is relatively simple, and the response speed can be achieved quickly, but there are some problems such as small dynamic range of output and low efficiency. Switching power supply has become the first choice for this, but how to achieve fast DVS response has been a big problem of switching power supply. For this reason, this paper presents the design method of a voltage-mode controlled step-down converter with fast DVS response, and designs and optimizes a voltage-mode controlled step-down converter with 5MHz switching frequency. In terms of design method, the influence of zero pole position on loop stability in three types compensation is analyzed, and a design example is given. In addition, the effects of complex poles, duty cycle saturation, inductance current saturation and pseudo-three-type compensation structure on DVS response are analyzed qualitatively. In the circuit design, this paper gives two chip design schemes. The two chips adopt different pseudo-three compensation schemes. One chip is optimized for the other chip and the performance is improved. The design of the first step-down converter is based on 0.13 渭 m standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1.2V-1.8V, and the maximum load current is 1A. The test results show that the upward tracking speed is 8.3 渭 s / V and the downward tracking speed is 15 渭 s / V when the DVS response occurs. The design of the second step-down converter is based on 40nm standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1V-2V, and the maximum load current is 1A. The simulation results show that the upward tracking speed is 3.7 渭 s / V and the downward tracking speed is 9.3 渭 s / V when DVS response occurs. The second chip adopts a new pseudo-three-type compensation topology, and the nonlinear method is used to effectively suppress the voltage downrush caused by the lower step response. Both chips use output capacitance of 4.7 渭 F and inductance of 1.1 渭 H with a switching frequency of 5 MHz. Finally, the chip verifies the proposed design method of the step-down converter with fast DVS response.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TM46
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相關(guān)碩士學(xué)位論文 前5條
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