本文選題：邏輯分析儀　切入點(diǎn)：虛擬儀器　出處：《吉林大學(xué)》2017年碩士論文

【摘要】：1973年,HP和IBM在合作的項(xiàng)目中研制成功了針對數(shù)字系統(tǒng)多個信號之間邏輯關(guān)系測試的儀器,隨后作為通用儀器被推廣開來,逐漸發(fā)展為邏輯分析儀,主要用于數(shù)字信號的顯示、分析、處理。邏輯分析儀的工作原理是采集數(shù)字信號,通過內(nèi)部、外部時鐘選擇分別進(jìn)行時序分析和狀態(tài)分析,同時依靠豐富的觸發(fā)功能對數(shù)據(jù)流進(jìn)行定位、分析時序錯誤。邏輯分析儀由采集電路、存儲器、主控制器、傳輸模塊、顯示部分等組成。由于單機(jī)版的邏輯分析儀售價昂貴,使用門檻過高,導(dǎo)致難以像示波器一樣普及,同時基于PC的虛擬邏輯分析儀發(fā)展迅速,成本相對低廉,功能上也能夠滿足一般的數(shù)字信號檢測需求。因而本文研究設(shè)計(jì)了以FPGA為主控制器的虛擬邏輯分析儀,具有采樣率高、存儲深度大、抗干擾能力強(qiáng)、升級靈活、方便攜帶、成本低廉等優(yōu)勢,能夠滿足測試基本數(shù)字信號的需求。虛擬邏輯分析系統(tǒng)是以Xilinx公司的XC6SLX45 FPGA現(xiàn)場可編程邏輯控制器為主控芯片,能夠?qū)崿F(xiàn)芯片功能的可重構(gòu)。它提供了極佳的低功耗和高性能之間的均衡性,通過內(nèi)存接口管理器連接一顆內(nèi)存容量為2Gb的SDRAM DDR3,用于對16通道數(shù)字信號進(jìn)行緩存處理,每通道能夠保證1MB的存儲深度。傳輸介質(zhì)采用USB總線,采用了Cypress公司的FX2LP USB微控制器,最終將數(shù)據(jù)傳輸?shù)缴衔粰C(jī)。人機(jī)界面由圖形化編程語言LabVIEW編寫,數(shù)字波形通過虛擬化的儀器界面展示,完整實(shí)現(xiàn)數(shù)字信號的采集、緩存、顯示、處理過程。LabVIEW程序開源,可由用戶重新構(gòu)建前面板和邏輯功能。經(jīng)調(diào)試表明,通道之間沒有干擾產(chǎn)生,波形能夠穩(wěn)定、準(zhǔn)確地觸發(fā)顯示,達(dá)到了設(shè)計(jì)之初的要求。
[Abstract]:In 1973, HP and IBM successfully developed an instrument to test the logic relationship between multiple signals in digital system, which was popularized as a universal instrument and developed into a logic analyzer, which is mainly used to display digital signals.Analysis, treatment.The working principle of the logic analyzer is to collect digital signals, analyze timing and state separately through internal and external clock selection, at the same time, rely on the rich trigger function to locate the data stream and analyze the timing errors.Logic analyzer is composed of acquisition circuit, memory, main controller, transmission module and display part.Because of the high price and high threshold of single machine version logic analyzer, it is difficult to be popularized as oscilloscope. At the same time, the virtual logic analyzer based on PC is developing rapidly and the cost is relatively low.Function can also meet the general needs of digital signal detection.Therefore, a virtual logic analyzer with FPGA as its main controller is designed in this paper, which has the advantages of high sampling rate, large storage depth, strong anti-interference ability, flexible upgrade, easy to carry, low cost, and so on.Able to meet the needs of testing basic digital signals.The virtual logic analysis system takes XC6SLX45 FPGA field programmable logic controller of Xilinx company as the main control chip, and can realize the function reconfiguration of the chip.It provides an excellent balance between low power consumption and high performance. A memory interface manager is used to connect a SDRAM DDR3 with memory capacity of 2Gb to cache 16-channel digital signals. Each channel can guarantee the storage depth of 1MB.The transmission medium adopts USB bus and FX2LP USB microcontroller of Cypress Company. Finally, the data is transferred to the host computer.The man-machine interface is written by the graphical programming language LabVIEW, the digital waveform is displayed through the virtualized instrument interface, the complete realization digital signal collection, the cache, the display, the processing process. LabVIEW program open source,The front panel and logic functions can be rebuilt by the user.The debugging results show that there is no interference between the channels, and the waveform can be triggered and displayed stably and accurately, which meets the requirements of the design at the beginning of the design.
【學(xué)位授予單位】：吉林大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TM935

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 殷曄;李麗斯;常路;尉曉惠;;基于FPGA的DDR3存儲控制的設(shè)計(jì)與驗(yàn)證[J];計(jì)算機(jī)測量與控制;2015年03期

2 薛騰飛;朱江;喬明;;一種滯回比較器設(shè)計(jì)[J];電子與封裝;2015年03期

3 李寶;劉志軒;徐進(jìn);陳東濤;李箭;;基于SDRAM的大容量FIFO的方案設(shè)計(jì)[J];導(dǎo)彈與航天運(yùn)載技術(shù);2014年04期

4 何鵬;劉一清;;基于Spartan-6 FPGA的DDR3布線分析和測試[J];電子測量技術(shù);2014年06期

5 劉繼磊;任虹霞;王新民;王冰;;基于FPGA的USB通信模塊在伺服系統(tǒng)中的應(yīng)用研究[J];微電機(jī);2011年11期

6 黃佳鈺;鄧焱;張錦杰;;嵌入式LabVIEW調(diào)用DLL實(shí)現(xiàn)數(shù)據(jù)采集[J];微計(jì)算機(jī)信息;2010年11期

7 王瑩;;可編程邏輯器件的歷程[J];電子產(chǎn)品世界;2009年11期

8 蔡共宣;;LabVIEW編程思想研究[J];裝備制造技術(shù);2009年09期

9 劉森;趙明生;;通過USB接口實(shí)現(xiàn)FPGA的SelectMap配置[J];微計(jì)算機(jī)信息;2009年11期

10 張億雄;顧海明;;基于調(diào)用DLL的LabVIEW數(shù)據(jù)采集的實(shí)現(xiàn)[J];微計(jì)算機(jī)信息;2008年34期

相關(guān)碩士學(xué)位論文 前7條

1 馬曉瑞;拖曳式成像聲納采集與傳輸系統(tǒng)硬件設(shè)計(jì)[D];浙江大學(xué);2015年

2 徐盛晨;基于FPGA的實(shí)時數(shù)據(jù)采集與傳輸系統(tǒng)的設(shè)計(jì)[D];北京郵電大學(xué);2014年

3 遲春華;基于虛擬儀器的電動汽車上位機(jī)遠(yuǎn)程監(jiān)控系統(tǒng)的設(shè)計(jì)[D];大連理工大學(xué);2012年

4 鞠佳勇;基于虛擬儀器技術(shù)的測灰儀上位機(jī)軟件開發(fā)[D];清華大學(xué);2012年

5 孫金寶;基于USB接口的虛擬邏輯分析儀的實(shí)現(xiàn)[D];西安電子科技大學(xué);2007年

6 韋建榮;可重構(gòu)測控系統(tǒng)的研究與設(shè)計(jì)[D];吉林大學(xué);2006年

7 任莉;基于USB2.0構(gòu)建分布式偏振耦合測試儀數(shù)據(jù)采集系統(tǒng)[D];天津大學(xué);2006年

，

本文編號：1718832