發(fā)布時(shí)間：2018-02-12 03:30

  本文關(guān)鍵詞： 低壓差線(xiàn)性穩(wěn)壓器 超低功耗 無(wú)片外電容 嵌套密勒補(bǔ)償 阻抗衰減緩沖器　出處：《浙江大學(xué)》2017年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：低壓差線(xiàn)性穩(wěn)壓器(low-dropout regulator,LDO)具有結(jié)構(gòu)簡(jiǎn)單、低噪聲、低功耗以及封裝尺寸小等突出優(yōu)點(diǎn),在便攜式電子產(chǎn)品中作為電源轉(zhuǎn)換電路得到廣泛的應(yīng)用。無(wú)片外電容LD0不需要外接特定的電容,也不需增加額外引腳,減小了芯片和PCB面積,從而成為近年來(lái)研究的熱點(diǎn)。本文著重研究與設(shè)計(jì)超低功耗無(wú)片外電容LDO,首先對(duì)實(shí)現(xiàn)超低功耗、無(wú)片外電容LDO的幾個(gè)關(guān)鍵問(wèn)題進(jìn)行了研究分析,主要針對(duì)超低功耗LDO如何分配電流、增強(qiáng)擺率以及無(wú)片外電容LDO如何補(bǔ)償頻率、改善瞬態(tài)特性等作出研究。并對(duì)低電壓帶隙基準(zhǔn)的設(shè)計(jì)、高擺率緩沖器的設(shè)計(jì)、頻率補(bǔ)償方式的分析,以及負(fù)載調(diào)整率的改善四個(gè)方面進(jìn)行了深入的理論研究和探討。最后利用上述的理論研究,設(shè)計(jì)了輸出電壓為1.5 V,最大輸出電流為1.5 mA,靜態(tài)電流為881 nA的無(wú)片外電容LDO。該LDO主環(huán)路采用三級(jí)運(yùn)放結(jié)構(gòu),將帶動(dòng)態(tài)偏置并聯(lián)反饋結(jié)構(gòu)的緩沖器作為中間級(jí)驅(qū)動(dòng)PMOS功率管。使用嵌套密勒補(bǔ)償方式(NMC),將低頻主極點(diǎn)放置在第一級(jí)輸出,將緩沖器輸出極點(diǎn)和LD0輸出極點(diǎn)作為次極點(diǎn)構(gòu)成極點(diǎn)-極點(diǎn)追蹤。芯片采用GSMC公司的130 nmCMOC工藝模型設(shè)計(jì)并經(jīng)流片測(cè)試。測(cè)試結(jié)果表明:在1.6～4.2V輸入電壓下,輸出1.5V電壓,最大輸出電流為1.5mA時(shí)靜態(tài)電流小于881 nA。當(dāng)負(fù)載電流在100 ns內(nèi)由1.5 mA到0跳變時(shí),輸出電壓變化小于95 mV;當(dāng)電源電壓在0.5 V范圍內(nèi)跳變時(shí),輸出電壓變化小于36 mV。測(cè)試結(jié)果驗(yàn)證了以上設(shè)計(jì)。
[Abstract]:Low voltage differential linear regulator (LDO) has the advantages of simple structure, low noise, low power consumption and small package size. It is widely used as a power conversion circuit in portable electronic products. The off-chip capacitive LD0 does not require specific external capacitors, nor does it require additional pins, thus reducing the area of chips and PCB. In this paper, we focus on the research and design of ultra-low power off-chip capacitors. Firstly, several key issues of realizing ultra-low power consumption and off-chip capacitance LDO are studied and analyzed. This paper mainly focuses on how to distribute current in ultra-low power LDO, how to increase swing rate, how to compensate frequency of LDO without chip capacitance, how to improve transient characteristic, and how to design low voltage bandgap reference and high swing buffer. The analysis of frequency compensation mode and the improvement of load adjustment rate are discussed in four aspects. The output voltage is 1.5 V, the maximum output current is 1.5 Ma, and the static current is 881nA. The main loop of the LDO is composed of three-stage operational amplifier, the output voltage is 1.5 V, the output current is 1.5 Ma, and the static current is 881nA. The buffer with dynamic offset parallel feedback structure is used as the intermediate stage driving PMOS power transistor. The low frequency main pole is placed in the first stage output by using the nested Miller compensation method. The buffer output pole and the LD0 output pole are used as the sub-poles to constitute the pole-pole tracking. The chip is designed by GSMC 130 nmCMOC process model and tested on the wafer. The test results show that the output voltage is 1.5V at 1.6V 4.2V input voltage. When the maximum output current is 1.5 Ma, the static current is less than 881nA. when the load current changes from 1.5 Ma to 0 in 100 ns, the output voltage changes less than 95 MV, and when the supply voltage is within 0.5 V, the output voltage changes less than 95 MV. The output voltage variation is less than 36 MV. The test results verify the above design.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TM44

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本文編號(hào)：1504686