【摘要】：網(wǎng)絡傳輸?shù)牧髅襟w技術已經(jīng)被廣泛應用到各個領域,現(xiàn)階段流媒體數(shù)據(jù)的實時傳輸主要依賴于操作系統(tǒng)來實現(xiàn),本論文設計實現(xiàn)了一個脫離主機操作系統(tǒng)、通過網(wǎng)絡接口即可獨立進行流媒體數(shù)據(jù)收發(fā)的IP核,有效地解決了網(wǎng)絡數(shù)據(jù)在收發(fā)過程中對主機處理器和存儲器資源的占用和浪費,提升了處理器的工作效率。 流媒體傳輸協(xié)議的IP核設計是以OSI開放系統(tǒng)互聯(lián)模型為基礎,深刻理解網(wǎng)絡協(xié)議的層次架構之后,采用FPGA自頂而下的模塊化設計理念,以網(wǎng)絡協(xié)議內(nèi)容為框架,對各協(xié)議層進行模塊化設計,而物理層部分采用單端口10/100Mbps收發(fā)器WJLXT972C. 網(wǎng)絡傳輸流媒體數(shù)據(jù)要進行應用層、網(wǎng)絡層、傳輸層和數(shù)據(jù)鏈路層等各協(xié)議層幀頭的封裝,各協(xié)議層模塊按功能劃分為控制模塊和數(shù)據(jù)通道。前者用多個狀態(tài)機的狀態(tài)跳轉(zhuǎn)來協(xié)同實現(xiàn)發(fā)送與接收控制,后者用FIFO進行數(shù)據(jù)的存儲,利用CRC校驗進行數(shù)據(jù)檢錯。 整個設計采用Xilinx公司的ISE軟件完成,用VHDL語言實現(xiàn)流媒體傳輸協(xié)議的IP核設計,各個協(xié)議層模塊附有狀態(tài)跳轉(zhuǎn)圖和結果分析圖。系統(tǒng)驗證采用Virtex-II開發(fā)板,通過RJ-45接口與PC端相連,將IP核傳輸來的流媒體數(shù)據(jù)在主機端進行數(shù)據(jù)接收和解碼顯示驗證。
[Abstract]:The streaming media technology of network transmission has been widely used in various fields. At present, the real-time transmission of streaming media data mainly depends on the operating system. In this paper, a separate host operating system is designed and implemented. The IP core of streaming media data receiving and receiving can be carried out independently through the network interface, which effectively solves the occupation and waste of host processor and memory resources in the process of receiving and receiving network data, and improves the working efficiency of the processor. The IP core design of streaming media transmission protocol is based on OSI open system interconnection model, deeply understands the hierarchical architecture of network protocol, adopts the modular design concept of FPGA from top to bottom, and takes the content of network protocol as the framework. The modularization design of each protocol layer is carried out, while the physical layer adopts single port 10/100Mbps transceiver WJLXT972C.. The transmission of streaming media data in the network should be packaged by the application layer, the network layer, the transport layer and the data link layer. Each protocol layer module is divided into control module and data channel according to its function. The former uses the state jump of multiple state machines to realize the transmission and reception control, while the latter uses FIFO for data storage and CRC verification for data error detection. The whole design is completed by ISE software of Xilinx Company, and the IP core design of streaming media transmission protocol is realized by VHDL language. each protocol layer module is equipped with state jump diagram and result analysis diagram. The system is verified by Virtex-II development board, connected with PC through RJ-45 interface, and the streaming media data transmitted by IP core is verified by data reception and decoding display on the host side.
【學位授予單位】：太原理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.04

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