【摘要】：隨著信息社會(huì)的發(fā)展,人們對(duì)計(jì)算機(jī)技術(shù)的高實(shí)時(shí)性和高可靠性的要求日益增長(zhǎng),加之芯片技術(shù)的不斷進(jìn)步,嵌入式計(jì)算技術(shù)將獲得廣闊的發(fā)展空間和應(yīng)用前景。目前,嵌入式計(jì)算技術(shù)已進(jìn)入工業(yè)控制、環(huán)境工程、信息家電和個(gè)人移動(dòng)數(shù)據(jù)處理等諸多領(lǐng)域,尤其是高性能嵌入式計(jì)算技術(shù),在國(guó)防、航天等重要領(lǐng)域發(fā)揮著重要作用。高性能嵌入式分布式集群系統(tǒng)的發(fā)展離不開高速總線電路的發(fā)展。在以高性能嵌入式計(jì)算技術(shù)構(gòu)建的綜合化信息處理系統(tǒng)中,為了實(shí)現(xiàn)數(shù)據(jù)的高速通信,采用串行RapidIO高速總線和萬兆以太網(wǎng)兩種協(xié)議分別作為射頻前端預(yù)處理和后端綜合顯控處理的數(shù)據(jù)交換網(wǎng)絡(luò),因此,面臨兩種協(xié)議之間的實(shí)時(shí)數(shù)據(jù)轉(zhuǎn)換問題。串行RapidIO由于使用高速串行技術(shù),并且擁有可以將多個(gè)處理器互聯(lián),使計(jì)算機(jī)集群化,云計(jì)算化、內(nèi)存共享等特點(diǎn),被廣泛運(yùn)用于嵌入式計(jì)算機(jī)的芯片間、板間通信互聯(lián)。目前,在嵌入式計(jì)算機(jī)領(lǐng)域及通信技術(shù)領(lǐng)域,RapidIO已逐漸成為新型多計(jì)算機(jī)、多處理器、多DSP的互聯(lián)的首要選擇。萬兆以太網(wǎng)是一種高速以太網(wǎng)接口,提供10Gbps的以太網(wǎng)帶寬的長(zhǎng)距離傳輸,被廣泛應(yīng)用于數(shù)據(jù)交換中心、數(shù)據(jù)視頻廣播等需要高帶寬數(shù)據(jù)的場(chǎng)合,并且可以有效實(shí)現(xiàn)網(wǎng)絡(luò)上大數(shù)據(jù)量匯聚和鏈路聚合。本文針對(duì)兩種協(xié)議之間的實(shí)時(shí)數(shù)據(jù)轉(zhuǎn)換問題,設(shè)計(jì)了一個(gè)串行RapidIO和萬兆以太網(wǎng)之間的路由控制接口,采用硬件設(shè)計(jì)技術(shù)實(shí)現(xiàn)了高速實(shí)時(shí)的數(shù)據(jù)傳輸通道,可以被廣泛應(yīng)用于綜合信息電子系統(tǒng),以及作為智能的IO接口模塊形式應(yīng)用于多個(gè)前端射頻預(yù)處理和核心處理機(jī)平臺(tái)中,用以解決嵌入式實(shí)時(shí)系統(tǒng)和后端任務(wù)信息處理系統(tǒng)的大數(shù)據(jù)實(shí)時(shí)交換問題,有很高的應(yīng)用價(jià)值。本文的主要工作包括：(1)設(shè)計(jì)了一個(gè)基于FPGA的串行RapidIO和萬兆以太網(wǎng)之間的路由控制接口,可在兩種協(xié)議之間實(shí)現(xiàn)數(shù)據(jù)包轉(zhuǎn)換的流水操作。該接口由一個(gè)4×SRIO接口、一個(gè)萬兆以太網(wǎng)接口和一個(gè)用戶調(diào)度邏輯模塊構(gòu)成,其中用戶調(diào)度邏輯模塊主要進(jìn)行兩部分處理：接收萬兆以太網(wǎng)傳來的數(shù)據(jù)包轉(zhuǎn)換為RapidIO郵箱消息與接收RapidIO郵箱消息轉(zhuǎn)換為以太網(wǎng)包。(2)使用RapidIO郵箱消息機(jī)制來處理不同協(xié)議之間的數(shù)據(jù)包轉(zhuǎn)換,將接收到的以太網(wǎng)包拆分成若干個(gè)消息段(segs),而將接收到的RapidIO郵箱消息組合成以太網(wǎng)包進(jìn)行發(fā)送。使用RapidIO Doorbell作為中斷,用來通知接收方發(fā)送已完成。在萬兆網(wǎng)轉(zhuǎn)RapidIO和RapidIO轉(zhuǎn)萬兆網(wǎng)兩個(gè)方向上,都采用可重傳超時(shí)錯(cuò)誤包的消息發(fā)送結(jié)構(gòu)。(3)在接收處理RapidIO郵箱消息時(shí),需要將消息存儲(chǔ)在FPGA上,等收齊一組消息后再按照以太網(wǎng)包的格式發(fā)送。為了區(qū)分消息內(nèi)容和其他郵箱消息,專門設(shè)計(jì)了16個(gè)郵箱模塊來進(jìn)行多組消息的整合,并通過比對(duì)消息長(zhǎng)度(Msglen)和消息標(biāo)識(shí)(Msgseg)來檢查一組消息是否發(fā)送完成。(4)使用物理地址與郵箱地址查找表寄存器組來配置萬兆以太網(wǎng)絡(luò)設(shè)備與RapidIO郵箱之間的匹配信息。同時(shí),采用RapidIO的NREAD和NWRITE操作對(duì)寄存器進(jìn)行相應(yīng)的維護(hù)與更改。
[Abstract]:With the development of the information society, people's demands for high real-time and high reliability of computer technology, and the progress of the chip technology, the embedded computing technology will have a wide development space and application prospect. At present, the embedded computing technology has entered the fields of industrial control, environmental engineering, information appliances and personal mobile data processing, especially high-performance embedded computing technology, and plays an important role in the important fields such as national defense and aerospace. The development of high-performance embedded distributed cluster system is based on the development of high-speed bus circuit. in a comprehensive information processing system constructed with high-performance embedded computing technology, in order to realize high-speed communication of data, two protocols of a serial RapidIO high-speed bus and a ten-gigabit Ethernet are adopted as a data exchange network of a radio-frequency front-end pre-processing and a back-end integrated display control process, The problem of real-time data conversion between the two protocols is faced. Serial RapidIO is widely used in inter-chip and inter-board communication of embedded computer due to the use of high-speed serial technology, and it has the characteristics of interconnection of multiple processors, computer clustering, cloud computing, and memory sharing. At present, in the field of embedded computer and communication technology, RapidIO has become the first choice for multi-computer, multi-processor and multi-DSP. The 10-Gigabit Ethernet is a high-speed Ethernet interface, which provides the long-distance transmission of 10Gbps Ethernet bandwidth, and is widely used in the field of data exchange center, data video broadcasting and the like, and can effectively realize the convergence and link aggregation of large data volume on the network. In order to solve the problem of real-time data conversion between two protocols, a route control interface between serial RapidIO and 10 Gigabit Ethernet is designed, and the high-speed real-time data transmission channel is realized by the hardware design technology, which can be widely used in the comprehensive information electronic system. and is applied to a plurality of front-end radio-frequency pre-processing and core processor platforms as an intelligent IO interface module, and is used for solving the problem of large-data real-time exchange of the embedded real-time system and the back-end task information processing system, and has high application value. The main work of this paper includes: (1) designing a routing control interface between serial RapidIO and 10 Gigabit Ethernet based on FPGA, and can realize the flow operation of data packet conversion between the two protocols. The interface consists of a 4-level SRIO interface, a ten-gigabit Ethernet interface and a user scheduling logic module, wherein the user scheduling logic module mainly performs two-part processing: The packet received from the 10 Gigabit Ethernet is converted to the RapidIO mailbox message and the received RapidIO mailbox message is converted to an Ethernet packet. (2) the RapidIO mailbox message mechanism is used for processing data packet conversion between different protocols, and the received Ethernet packet is split into a plurality of message segments (segs), and the received RapidIO mailbox message is combined into an Ethernet packet for transmission. Use RapidIO Doorbell as an interrupt to inform the recipient that the transmission has been completed. The message transmission structure of the retransmission time-out error packet is used in both directions of the 10-mega-net-to-RapidIO and the RapidIO-M-M network. and (3) when the RapidIO mailbox message is received, the message needs to be stored on the FPGA, and after the group of messages is received, the message is sent according to the format of the Ethernet packet. in order to distinguish the message content and other mailbox messages, 16 mailbox modules are specifically designed to complete the multiple sets of messages and check whether a set of messages is sent by a comparison of the message length (Msglen) and the message identity (Msgseg). and (4) using a physical address and an e-mail address lookup table register group to configure the matching information between the ten-gigabit Ethernet network device and the RapidIO mailbox. At the same time, the registers are maintained and changed with the NREAD and NWRITE operations of RapidIO.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP393.11;TP393.05

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