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基于NetFPGA 10G的PON系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)

發(fā)布時(shí)間:2018-11-14 07:38
【摘要】:隨著科技的進(jìn)步與信息產(chǎn)業(yè)的發(fā)展,人們對(duì)網(wǎng)絡(luò)服務(wù)質(zhì)量及網(wǎng)絡(luò)帶寬的需求隨之提高。然而近年來(lái)核心網(wǎng)帶寬增長(zhǎng)迅速,核心網(wǎng)與用戶(hù)之間的接入網(wǎng)發(fā)展卻相對(duì)滯后。作為光纖接入技術(shù)之一的以太無(wú)源光網(wǎng)絡(luò)(Ethernet Passive OpticalNetwork, EPON)技術(shù)有效利用了現(xiàn)有以太網(wǎng)的寶貴資源,并具有成本低、帶寬高、維護(hù)簡(jiǎn)單等優(yōu)點(diǎn),,被認(rèn)為是解決“最后一公里”問(wèn)題的最佳方案之一。 NetFPGA是斯坦福大學(xué)設(shè)計(jì)開(kāi)發(fā)的低成本開(kāi)源性網(wǎng)絡(luò)測(cè)試平臺(tái),該平臺(tái)既具有硬件的高速處理性,又具備軟件可編程、可重用的靈活性。本文分析了EPON系統(tǒng)現(xiàn)有仿真環(huán)境,并對(duì)EPON的關(guān)鍵技術(shù)及NetFPGA10G平臺(tái)的應(yīng)用與開(kāi)發(fā)進(jìn)行了深入研究,提出了一種基于NetFPGA10G平臺(tái)的PON系統(tǒng)設(shè)計(jì)方案。本文的主要研究?jī)?nèi)容如下: (1)對(duì)EPON系統(tǒng)與NetFPGA10G平臺(tái)的研究背景及國(guó)內(nèi)外研究現(xiàn)狀進(jìn)行了深入調(diào)研。介紹了EPON系統(tǒng)的層次模型與工作原理,并對(duì)EPON現(xiàn)有的仿真環(huán)境進(jìn)行了分析,探討了在NetFPGA10G平臺(tái)上實(shí)現(xiàn)PON系統(tǒng)原型搭建的必要性。 (2)對(duì)NetFPGA10G數(shù)據(jù)通路的功能模塊進(jìn)行了介紹,深入分析了數(shù)據(jù)處理流程,并針對(duì)模塊間通信問(wèn)題對(duì)AXI4-Stream總線進(jìn)行了研究。 (3)針對(duì)EPON系統(tǒng)中的光線路終端(Optical Line Terminal, OLT)與光網(wǎng)絡(luò)單元(Optical Network Unit, ONU)功能的差異分別給出了其設(shè)計(jì)方案,該方案選用與PON系統(tǒng)工作在OSI參考模型的相同層面,且結(jié)構(gòu)最為簡(jiǎn)潔的Reference NIC作為參考工程;采用模塊化設(shè)計(jì)思想,降低了功能模塊實(shí)現(xiàn)的復(fù)雜度;編程過(guò)程中采用三段式狀態(tài)機(jī),減少了輸入信號(hào)對(duì)輸出信號(hào)的干擾;核心處理模塊采用后端緩存機(jī)制,以便對(duì)上下行數(shù)據(jù)傳輸時(shí)隙的控制。 本方案采用Verilog HDL進(jìn)行編程,結(jié)合ISE、XPS等工具將OLT/ONU核心模塊嵌入至NetFPGA10G數(shù)據(jù)通路中,實(shí)現(xiàn)了EPON系統(tǒng)的上下行數(shù)據(jù)通路、MPCP協(xié)議及以太網(wǎng)交換功能,并對(duì)所實(shí)現(xiàn)的EPON系統(tǒng)進(jìn)行了仿真驗(yàn)證。
[Abstract]:With the progress of science and technology and the development of information industry, the demand for network service quality and network bandwidth has been improved. However, the bandwidth of core network grows rapidly in recent years, but the access network between core network and user lags behind. As one of the optical fiber access technologies, the Ethernet passive optical network (Ethernet Passive OpticalNetwork, EPON) technology effectively utilizes the valuable resources of the existing Ethernet, and has the advantages of low cost, high bandwidth, simple maintenance and so on. Is considered to be one of the best solutions to the "last kilometer" problem. NetFPGA is a low cost open source network testing platform designed and developed by Stanford University. The platform not only has the high speed processing of hardware, but also has the flexibility of software programmable and reusable. In this paper, the existing simulation environment of EPON system is analyzed, the key technology of EPON and the application and development of NetFPGA10G platform are deeply studied, and a design scheme of PON system based on NetFPGA10G platform is put forward. The main contents of this paper are as follows: (1) the research background of EPON system and NetFPGA10G platform and the current research situation at home and abroad have been deeply investigated. This paper introduces the hierarchical model and working principle of EPON system, analyzes the existing simulation environment of EPON, and discusses the necessity of building prototype of PON system on NetFPGA10G platform. (2) the function module of NetFPGA10G data path is introduced, the data processing flow is deeply analyzed, and the AXI4-Stream bus is studied for the communication between modules. (3) according to the difference of the function between the optical line terminal (Optical Line Terminal, OLT) and the optical network unit (Optical Network Unit, ONU) in the EPON system, the design scheme is given respectively. The scheme is chosen to work on the same level as the PON system in the OSI reference model. And the structure of the most concise Reference NIC as a reference project; The modularization design idea is adopted to reduce the complexity of the function module, and the three-stage state machine is used in the programming process, which reduces the interference of the input signal to the output signal. The core processing module adopts back-end buffer mechanism to control the time slot of data transmission. This scheme uses Verilog HDL to program, combines ISE,XPS and other tools to embed the core module of OLT/ONU into the NetFPGA10G data path, realizes the up / down data path of EPON system, MPCP protocol and Ethernet exchange function. The EPON system is simulated and verified.
【學(xué)位授予單位】:河北工程大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類(lèi)號(hào)】:TP393.11

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