基于FPGA及以太網(wǎng)技術(shù)的100G接口板設(shè)計
發(fā)布時間：2018-10-10 11:32
【摘要】：近年來,隨著IT行業(yè)的高速發(fā)展,高清視頻、虛擬化、電子商務(wù)、無線3G以及4G網(wǎng)絡(luò)等各種新興業(yè)務(wù)不斷涌現(xiàn),人們對于網(wǎng)絡(luò)帶寬的需求正在飛速增長,而云計算的出現(xiàn)及部署更加速了人們對網(wǎng)絡(luò)帶寬需求的增長,這勢必導致網(wǎng)絡(luò)匯聚節(jié)點網(wǎng)絡(luò)帶寬的成倍增長。高端路由器作為在數(shù)據(jù)中心和骨干網(wǎng)絡(luò)層使用的關(guān)鍵互聯(lián)設(shè)備,其10G端口已不能滿足業(yè)務(wù)對于帶寬的需求,研究和開發(fā)支持100G端口的以太網(wǎng)設(shè)備就變得十分必要和迫切了。 以往的以太網(wǎng)設(shè)備,多是以專用的網(wǎng)絡(luò)處理芯片為主體設(shè)計的,而專用芯片的設(shè)計不夠靈活、移植性不強,而且價格昂貴,導致以太網(wǎng)設(shè)備成本高。本文結(jié)合可編程邏輯器件設(shè)計靈活、可移植性強的特點,采用Altera公司最新StratixV可編程邏輯器件,設(shè)計一套以兩片F(xiàn)PGA為主體的系統(tǒng)方案,兩片F(xiàn)PGA分別進行包處理和流量管理,可實現(xiàn)完善的100G路由轉(zhuǎn)發(fā)功能。 硬件設(shè)計部分對系統(tǒng)的主要功能模塊：MPU模塊、FPGA模塊、CFP模塊以及電源和時鐘模塊進行詳細設(shè)計。理論研究在參閱了IEEE802.3ba標準及其相關(guān)會議文稿的基礎(chǔ)上,對100G以太網(wǎng)物理層架構(gòu)及其實現(xiàn)上進行深入研究,詳細闡述64B/66B的編解碼、并行自同步擾解碼以及PCS層MLD通道分發(fā)機制的原理,并用verilogHDL語言對其進行設(shè)計,在modelsim上對其各個部分進行仿真,驗證邏輯設(shè)計的正確性。 最后在系統(tǒng)層面上對其進行測試設(shè)計,結(jié)合100G CFP光模塊,用spirent公司的testcenter專業(yè)打流測試儀對100G接口板進行實際場景測試,驗證系統(tǒng)設(shè)計的正確性。
[Abstract]:In recent years, with the rapid development of IT industry, high definition video, virtualization, e-commerce, wireless 3G and 4G network and other emerging services, people's demand for network bandwidth is growing rapidly. The emergence and deployment of cloud computing accelerates the growth of network bandwidth demand, which will inevitably lead to the multiple growth of network bandwidth of network convergence node. As the key interconnection equipment used in data center and backbone network layer, the 10G port of high-end router can no longer meet the bandwidth requirement of service, so it is necessary and urgent to research and develop the Ethernet device which supports 100G port. In the past, most Ethernet devices were designed with special network processing chip as the main body, but the design of special Ethernet chip was not flexible, portability was not strong, and the price was high, which led to the high cost of Ethernet equipment. According to the characteristics of flexible design and strong portability of programmable logic devices, this paper uses the latest StratixV programmable logic devices of Altera Company to design a system with two pieces of FPGA as the main part. The two pieces of FPGA are used for packet processing and flow management, respectively. Can achieve a perfect 100 G routing forwarding function. In the part of hardware design, the main function module of the system is: 1. MPU module, FPGA module, CFP module, power supply module and clock module. On the basis of referring to the IEEE802.3ba standard and the related conference papers, the theoretical research has carried on the thorough research to the 100G Ethernet physical layer architecture and its realization, elaborated the 64B/66B codec in detail, The principle of parallel auto-synchronous scrambling decoding and MLD channel distribution in PCS layer is designed with verilogHDL language. The simulation of each part on modelsim is carried out to verify the correctness of the logic design. Finally, it is tested and designed at the system level. The 100G interface board is tested with the 100G CFP optical module and the 100G interface board is tested by the testcenter professional streaming tester of spirent Company, which verifies the correctness of the system design.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.11
本文編號：2261610
[Abstract]:In recent years, with the rapid development of IT industry, high definition video, virtualization, e-commerce, wireless 3G and 4G network and other emerging services, people's demand for network bandwidth is growing rapidly. The emergence and deployment of cloud computing accelerates the growth of network bandwidth demand, which will inevitably lead to the multiple growth of network bandwidth of network convergence node. As the key interconnection equipment used in data center and backbone network layer, the 10G port of high-end router can no longer meet the bandwidth requirement of service, so it is necessary and urgent to research and develop the Ethernet device which supports 100G port. In the past, most Ethernet devices were designed with special network processing chip as the main body, but the design of special Ethernet chip was not flexible, portability was not strong, and the price was high, which led to the high cost of Ethernet equipment. According to the characteristics of flexible design and strong portability of programmable logic devices, this paper uses the latest StratixV programmable logic devices of Altera Company to design a system with two pieces of FPGA as the main part. The two pieces of FPGA are used for packet processing and flow management, respectively. Can achieve a perfect 100 G routing forwarding function. In the part of hardware design, the main function module of the system is: 1. MPU module, FPGA module, CFP module, power supply module and clock module. On the basis of referring to the IEEE802.3ba standard and the related conference papers, the theoretical research has carried on the thorough research to the 100G Ethernet physical layer architecture and its realization, elaborated the 64B/66B codec in detail, The principle of parallel auto-synchronous scrambling decoding and MLD channel distribution in PCS layer is designed with verilogHDL language. The simulation of each part on modelsim is carried out to verify the correctness of the logic design. Finally, it is tested and designed at the system level. The 100G interface board is tested with the 100G CFP optical module and the 100G interface board is tested by the testcenter professional streaming tester of spirent Company, which verifies the correctness of the system design.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.11
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