基于NetFPGA的路由器功耗優(yōu)化研究
發(fā)布時(shí)間：2018-10-08 18:56
【摘要】：在21世紀(jì)，隨著科學(xué)技術(shù)的日益發(fā)展，互聯(lián)網(wǎng)已經(jīng)應(yīng)用于世界的各個(gè)領(lǐng)域。網(wǎng)絡(luò)互連設(shè)備作為構(gòu)成互聯(lián)網(wǎng)的重要組成部分，其數(shù)量飛速增長(zhǎng)，伴隨產(chǎn)生的功耗更是不可小視。而在眾多網(wǎng)絡(luò)互連設(shè)備中，路由器能將不同網(wǎng)絡(luò)或者網(wǎng)段之間的數(shù)據(jù)信息根據(jù)路由選擇協(xié)議進(jìn)行選擇而實(shí)現(xiàn)轉(zhuǎn)發(fā)，成為了最重要的網(wǎng)絡(luò)互連設(shè)備之一，在全球網(wǎng)絡(luò)運(yùn)行中產(chǎn)生的功耗也是十分巨大的。與此同時(shí)，出于經(jīng)濟(jì)和環(huán)境方面的考慮，在下一代網(wǎng)絡(luò)的研究中已經(jīng)把能源的充分利用放在越來(lái)越重要的地位。因此，通過(guò)對(duì)路由器結(jié)構(gòu)的研究來(lái)降低工作時(shí)產(chǎn)生的功耗具有較大的研究?jī)r(jià)值。 本文首先對(duì)路由器功耗優(yōu)化的研究背景進(jìn)行了介紹，分析了國(guó)內(nèi)外研究現(xiàn)狀，包括在NetFPGA開發(fā)平臺(tái)上的研究成果以及對(duì)于路由器功耗方面的研究狀況，從而論證了本課題具有一定的可研究性和創(chuàng)新性；之后對(duì)基于NetFPGA開發(fā)平臺(tái)的基本路由器的工作原理和內(nèi)部結(jié)構(gòu)進(jìn)行了深入的研究分析，同時(shí)在此基礎(chǔ)上通過(guò)硬件設(shè)計(jì)實(shí)現(xiàn)了根據(jù)流量自適應(yīng)調(diào)頻的路由器，包括根據(jù)外部數(shù)據(jù)流量統(tǒng)計(jì)和路由器內(nèi)部緩存區(qū)緩存量統(tǒng)計(jì)兩種實(shí)現(xiàn)自適應(yīng)調(diào)頻方式；最后通過(guò)使用功耗測(cè)試儀器對(duì)路由器各種頻率下所產(chǎn)生的功耗進(jìn)行測(cè)試與比較得出結(jié)論。 在深入研究基于NetFPGA開發(fā)平臺(tái)的基本路由器的工作原理和內(nèi)部結(jié)構(gòu)后，本文設(shè)計(jì)了一種根據(jù)流量自適應(yīng)調(diào)頻的路由器來(lái)降低其產(chǎn)生的功耗。并提出了根據(jù)路由器內(nèi)部緩存區(qū)緩存量統(tǒng)計(jì)和根據(jù)外部數(shù)據(jù)流量統(tǒng)計(jì)兩種實(shí)現(xiàn)自適應(yīng)調(diào)頻方式，前者是設(shè)計(jì)了一種緩存流量感知算法來(lái)統(tǒng)計(jì)當(dāng)前通過(guò)路由器流量的大小，后者是設(shè)計(jì)了外部接口數(shù)據(jù)統(tǒng)計(jì)模塊來(lái)統(tǒng)計(jì)當(dāng)前通過(guò)路由器流量的大小。與此同時(shí)，對(duì)根據(jù)流量自適應(yīng)調(diào)頻的路由器進(jìn)行了硬件電路的設(shè)計(jì)，包括多頻率產(chǎn)生電路，協(xié)調(diào)SRAM讀寫電路，兩種調(diào)頻機(jī)制硬件實(shí)現(xiàn)電路等。最終通過(guò)搭建的國(guó)際上領(lǐng)先的路由器功耗測(cè)試平臺(tái)，測(cè)試兩種調(diào)頻機(jī)制下路由器功耗優(yōu)化的情況。由于在大部分情況下單位時(shí)間內(nèi)通過(guò)路由器的流量都較小，因此本文設(shè)計(jì)的根據(jù)流量自適應(yīng)調(diào)頻路由器都能工作在較小的頻率下，，根據(jù)實(shí)驗(yàn)結(jié)果所得，在較低工作頻率下工作時(shí)路由器產(chǎn)生的功耗比原先不能調(diào)頻的路由器下降低15%-20%，有效的降低了路由器產(chǎn)生的功耗。 目前，對(duì)于路由器功耗的研究國(guó)內(nèi)外均有相關(guān)涉及，然而本文提出的根據(jù)流量自適應(yīng)調(diào)頻路由器的硬件電路設(shè)計(jì)尚未有相關(guān)文獻(xiàn)提出，并且本實(shí)驗(yàn)以及功耗測(cè)試平臺(tái)也具有一定的先進(jìn)行，因此對(duì)該課題的研究有一定創(chuàng)新意義。
[Abstract]:In the 21 st century, with the development of science and technology, the Internet has been applied in every field of the world. As an important part of the Internet, network interconnection devices are increasing rapidly, and the accompanying power consumption can not be underestimated. Among the many network interconnection devices, routers can select and forward the data information between different networks or network segments according to routing protocols, so they become one of the most important network interconnection devices. The power consumption generated in the global network operation is also very large. At the same time, due to economic and environmental considerations, the full use of energy has become more and more important in the next generation network (NGN) research. Therefore, it is of great value to study the structure of router to reduce the power consumption. This paper first introduces the research background of router power optimization, and analyzes the research status at home and abroad, including the research results on NetFPGA development platform and the research status of router power consumption. This paper demonstrates that this subject has certain researchability and innovation, and then makes a deep research and analysis on the working principle and internal structure of the basic router based on NetFPGA development platform. At the same time, the router which adapts to frequency modulation according to the traffic is realized by hardware design, including two ways of realizing adaptive frequency modulation according to the statistics of external data traffic and the cache of the inner buffer of router. Finally, the power consumption generated by the router at various frequencies is tested and compared with the power consumption test instrument. After deeply studying the working principle and internal structure of the basic router based on the NetFPGA development platform, this paper designs a router that adapts to frequency modulation according to the traffic to reduce its power consumption. This paper also proposes two ways to realize adaptive frequency modulation according to the statistics of internal buffer cache and external data traffic. The former is to design a cache traffic sensing algorithm to calculate the current traffic through the router. The latter is the design of external interface data statistics module to count the current traffic through the router size. At the same time, the hardware circuit of the router based on the traffic adaptive frequency modulation is designed, including the multi-frequency generation circuit, the coordinated SRAM reading and writing circuit, the hardware realization circuit of two kinds of FM mechanism and so on. Finally, the router power optimization under two frequency modulation mechanisms is tested by a leading international router power test platform. Because the traffic per unit time is smaller in most cases, the adaptive FM router designed in this paper can work at a lower frequency, according to the experimental results, When the router works at a lower operating frequency, the power consumption generated by the router is 15 to 20 lower than that under the original router without frequency modulation, which effectively reduces the power consumption generated by the router. At present, the research on router power consumption is related at home and abroad. However, the hardware circuit design of adaptive frequency modulation router based on traffic has not been proposed in this paper. And this experiment and the power consumption test platform also has certain first, therefore the research to this topic has the certain innovation significance.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP393.05
本文編號(hào)：2257901
[Abstract]:In the 21 st century, with the development of science and technology, the Internet has been applied in every field of the world. As an important part of the Internet, network interconnection devices are increasing rapidly, and the accompanying power consumption can not be underestimated. Among the many network interconnection devices, routers can select and forward the data information between different networks or network segments according to routing protocols, so they become one of the most important network interconnection devices. The power consumption generated in the global network operation is also very large. At the same time, due to economic and environmental considerations, the full use of energy has become more and more important in the next generation network (NGN) research. Therefore, it is of great value to study the structure of router to reduce the power consumption. This paper first introduces the research background of router power optimization, and analyzes the research status at home and abroad, including the research results on NetFPGA development platform and the research status of router power consumption. This paper demonstrates that this subject has certain researchability and innovation, and then makes a deep research and analysis on the working principle and internal structure of the basic router based on NetFPGA development platform. At the same time, the router which adapts to frequency modulation according to the traffic is realized by hardware design, including two ways of realizing adaptive frequency modulation according to the statistics of external data traffic and the cache of the inner buffer of router. Finally, the power consumption generated by the router at various frequencies is tested and compared with the power consumption test instrument. After deeply studying the working principle and internal structure of the basic router based on the NetFPGA development platform, this paper designs a router that adapts to frequency modulation according to the traffic to reduce its power consumption. This paper also proposes two ways to realize adaptive frequency modulation according to the statistics of internal buffer cache and external data traffic. The former is to design a cache traffic sensing algorithm to calculate the current traffic through the router. The latter is the design of external interface data statistics module to count the current traffic through the router size. At the same time, the hardware circuit of the router based on the traffic adaptive frequency modulation is designed, including the multi-frequency generation circuit, the coordinated SRAM reading and writing circuit, the hardware realization circuit of two kinds of FM mechanism and so on. Finally, the router power optimization under two frequency modulation mechanisms is tested by a leading international router power test platform. Because the traffic per unit time is smaller in most cases, the adaptive FM router designed in this paper can work at a lower frequency, according to the experimental results, When the router works at a lower operating frequency, the power consumption generated by the router is 15 to 20 lower than that under the original router without frequency modulation, which effectively reduces the power consumption generated by the router. At present, the research on router power consumption is related at home and abroad. However, the hardware circuit design of adaptive frequency modulation router based on traffic has not been proposed in this paper. And this experiment and the power consumption test platform also has certain first, therefore the research to this topic has the certain innovation significance.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP393.05
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