千兆以太網(wǎng)IEEE 1588協(xié)議的實現(xiàn)
發(fā)布時間：2018-09-12 17:30
【摘要】：隨著網(wǎng)絡(luò)技術(shù)的蓬勃發(fā)展,以太網(wǎng)以其協(xié)議通用性、遠(yuǎn)距離傳輸、靈活的網(wǎng)絡(luò)拓?fù)湟约安粩喟l(fā)展的網(wǎng)絡(luò)帶寬等諸多優(yōu)勢,被廣泛應(yīng)用到測試領(lǐng)域。網(wǎng)絡(luò)化自動測試系統(tǒng)主要針對分布式測試任務(wù),與以太網(wǎng)普通應(yīng)用相比,需實現(xiàn)控制操作的精確性和采集數(shù)據(jù)的時序關(guān)聯(lián)性。IEEE 1588協(xié)議標(biāo)準(zhǔn)是網(wǎng)絡(luò)化自動測試系統(tǒng)中實現(xiàn)測試設(shè)備及測試數(shù)據(jù)精密同步的重要方式。隨著被測目標(biāo)的測試復(fù)雜度和測試內(nèi)容的持續(xù)增長,百兆以太網(wǎng)已很難適應(yīng)系統(tǒng)對數(shù)據(jù)傳輸?shù)男枨?千兆以太網(wǎng)接口已成為未來網(wǎng)絡(luò)化測試設(shè)備的重要形式。本文在總結(jié)當(dāng)前主流的PTP(Precision Time Protocol)硬件支持方式的基礎(chǔ)上,以Xilinx Zynq-7000 SOC作為硬件設(shè)計平臺,深入分析比較了基于該硬件平臺的三種PTP硬件支持方案,以通用性和可擴展性為主要考量因素,設(shè)計了一種基于PL(Programmable Logic)自研IP核實現(xiàn)千兆以太網(wǎng)下IEEE 1588協(xié)議的方案框架。本方案為搭建網(wǎng)絡(luò)通信鏈路,設(shè)計了基于FMC接口的千兆以太網(wǎng)PHY硬件電路和屏蔽底層影響的速率選擇與數(shù)據(jù)優(yōu)化IP核,并開發(fā)相應(yīng)的通信測試工程測試了PHY與PS(Processing System)之間的通信功能。為完成PTP硬件支持,本方案在可編程邏輯器件中設(shè)計可配置實時時鐘和時間戳模塊,為上層設(shè)計提供了完備的時鐘調(diào)節(jié)接口,完成IEEE 1588實現(xiàn)亞微秒級同步精度所需的硬件支持,不要求在通信鏈路中配備支持硬件時間戳功能的PHY或MAC器件。上層設(shè)計采用在Linux操作系統(tǒng)中移植并優(yōu)化PTPd開源軟件并開發(fā)IP核設(shè)備驅(qū)動程序?qū)崿F(xiàn)IEEE 1588狀態(tài)機和硬件時間戳獲取功能,本方案可以直接移植到包含可編程邏輯器件和支持Linux的微處理器的儀器控制架構(gòu)中。在本方案的測試中,利用主從時鐘輸出秒脈沖信號(PPS),精確測試網(wǎng)絡(luò)節(jié)點設(shè)備的時鐘同步精度,本文從功能性和應(yīng)用性兩方面對本方案同步精度進行測試,分析設(shè)備時鐘頻率偏移、分布時鐘節(jié)點數(shù)、交換機轉(zhuǎn)發(fā)次數(shù)以及網(wǎng)絡(luò)背景流量對同步精度的影響,驗證了在經(jīng)多次交換機轉(zhuǎn)發(fā)并存在一定背景流量下的網(wǎng)絡(luò)化測試系統(tǒng)中保持各網(wǎng)絡(luò)節(jié)點設(shè)備亞微秒級同步精度的可行性。
[Abstract]:With the rapid development of network technology, Ethernet has been widely used in the field of testing for its advantages of universal protocol, long-distance transmission, flexible network topology and continuous development of network bandwidth. The networked automatic test system is mainly aimed at distributed testing tasks, compared with Ethernet applications. The precision of control operation and the timing correlation of data collected. IEEE 1588 protocol standard is an important way to realize precision synchronization of test equipment and test data in networked automatic test system. With the increasing of test complexity and test content, it is very difficult to adapt to the requirement of data transmission. Gigabit Ethernet interface has become an important form of networked test equipment in the future. On the basis of summing up the current mainstream PTP (Precision Time Protocol) hardware support methods and taking Xilinx Zynq-7000 SOC as the hardware design platform, this paper deeply analyzes and compares three kinds of PTP hardware support schemes based on this hardware platform. Taking generality and extensibility as the main consideration, a scheme framework for implementing IEEE 1588 protocol under Gigabit Ethernet based on PL (Programmable Logic) self-developed IP core is designed. In order to build the network communication link, the PHY hardware circuit of Gigabit Ethernet based on FMC interface is designed, and the rate selection and data optimization IP core of shielding the influence of the bottom layer are designed. The corresponding communication test project is developed to test the communication function between PHY and PS (Processing System). In order to complete PTP hardware support, this scheme designs configurable real-time clock and timestamp modules in programmable logic devices, provides a complete clock adjusting interface for the upper layer design, and accomplishes the hardware support required by IEEE 1588 to realize sub-microsecond synchronization precision. PHY or MAC devices that support hardware timestamp functionality are not required in communication links. The upper design adopts porting and optimizing PTPd open source software in Linux operating system and developing IP nuclear device driver to realize IEEE 1588 state machine and hardware timestamp acquisition function. This scheme can be directly transplanted to the instrument control architecture including programmable logic devices and microprocessors supporting Linux. In the test of this scheme, the clock synchronization accuracy of network node equipment is accurately tested by (PPS), which is used to output the second pulse signal from the master slave clock. The synchronization accuracy of this scheme is tested from the aspects of function and application. The effects of device clock frequency offset, number of distributed clock nodes, switch forwarding times and network background flow on synchronization accuracy are analyzed. The feasibility of maintaining the sub-microsecond synchronization accuracy of each network node equipment in the networked test system which is forwarded by multiple switches and has a certain background flow is verified.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP393.11
，
本文編號：2239740
[Abstract]:With the rapid development of network technology, Ethernet has been widely used in the field of testing for its advantages of universal protocol, long-distance transmission, flexible network topology and continuous development of network bandwidth. The networked automatic test system is mainly aimed at distributed testing tasks, compared with Ethernet applications. The precision of control operation and the timing correlation of data collected. IEEE 1588 protocol standard is an important way to realize precision synchronization of test equipment and test data in networked automatic test system. With the increasing of test complexity and test content, it is very difficult to adapt to the requirement of data transmission. Gigabit Ethernet interface has become an important form of networked test equipment in the future. On the basis of summing up the current mainstream PTP (Precision Time Protocol) hardware support methods and taking Xilinx Zynq-7000 SOC as the hardware design platform, this paper deeply analyzes and compares three kinds of PTP hardware support schemes based on this hardware platform. Taking generality and extensibility as the main consideration, a scheme framework for implementing IEEE 1588 protocol under Gigabit Ethernet based on PL (Programmable Logic) self-developed IP core is designed. In order to build the network communication link, the PHY hardware circuit of Gigabit Ethernet based on FMC interface is designed, and the rate selection and data optimization IP core of shielding the influence of the bottom layer are designed. The corresponding communication test project is developed to test the communication function between PHY and PS (Processing System). In order to complete PTP hardware support, this scheme designs configurable real-time clock and timestamp modules in programmable logic devices, provides a complete clock adjusting interface for the upper layer design, and accomplishes the hardware support required by IEEE 1588 to realize sub-microsecond synchronization precision. PHY or MAC devices that support hardware timestamp functionality are not required in communication links. The upper design adopts porting and optimizing PTPd open source software in Linux operating system and developing IP nuclear device driver to realize IEEE 1588 state machine and hardware timestamp acquisition function. This scheme can be directly transplanted to the instrument control architecture including programmable logic devices and microprocessors supporting Linux. In the test of this scheme, the clock synchronization accuracy of network node equipment is accurately tested by (PPS), which is used to output the second pulse signal from the master slave clock. The synchronization accuracy of this scheme is tested from the aspects of function and application. The effects of device clock frequency offset, number of distributed clock nodes, switch forwarding times and network background flow on synchronization accuracy are analyzed. The feasibility of maintaining the sub-microsecond synchronization accuracy of each network node equipment in the networked test system which is forwarded by multiple switches and has a certain background flow is verified.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP393.11
，
本文編號：2239740
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