【摘要】：光纖傳輸利用新一代的光纖作為傳輸介質(zhì)，具有傳輸速度快、數(shù)據(jù)帶寬高、傳輸距離遠(yuǎn)、信號(hào)損耗很低等優(yōu)點(diǎn)，適合大容量數(shù)據(jù)的遠(yuǎn)距離高速傳輸。而且在信息傳輸安全方面看，也比其他傳輸技術(shù)高的多。數(shù)字相機(jī)以CCD或CMOS作為成像介質(zhì)，能將光信號(hào)有效的轉(zhuǎn)換為電信號(hào)，便于后期的傳輸及處理，現(xiàn)已獲得極大的應(yīng)用。 以太網(wǎng)技術(shù)從一推出開(kāi)始就顯示出了強(qiáng)大的生命力并獲得了巨大的發(fā)展，利用以太網(wǎng)帶寬大的優(yōu)勢(shì)來(lái)傳輸高質(zhì)量的圖像數(shù)據(jù)變得越來(lái)越有誘惑力。其他傳輸協(xié)議與以太網(wǎng)相比起來(lái)，其帶寬仍然相對(duì)較小，數(shù)據(jù)傳輸速率相對(duì)較低，無(wú)法滿足高質(zhì)量圖像高速傳輸?shù)囊�。以太網(wǎng)技術(shù)可以很好的滿足這一要求，實(shí)現(xiàn)了大量數(shù)據(jù)的高速傳輸。 本文正是利用千兆光纖以太網(wǎng)來(lái)傳輸數(shù)字相機(jī)數(shù)據(jù)，以獲得數(shù)據(jù)的高速傳輸。同時(shí)采用FPGA來(lái)實(shí)現(xiàn)以太網(wǎng)協(xié)議，提高了系統(tǒng)的可移植性和靈活性，并為以后系統(tǒng)的升級(jí)帶來(lái)了方便。本文首先介紹了數(shù)字相機(jī)的工作原理以及光纖傳輸?shù)睦碚摶A(chǔ)，其次完成了系統(tǒng)所用電路板的設(shè)計(jì)工作，介紹了電路板各個(gè)模塊的電路原理圖設(shè)計(jì)方法，包括所用器件的選擇和使用，重點(diǎn)介紹了FPGA芯片和物理層芯片88E1111的原理和使用，利用硬件配置方法對(duì)88E1111芯片的工作模式進(jìn)行了配置。再次，著重介紹了在FPGA中基于VHDL語(yǔ)言實(shí)現(xiàn)了以太網(wǎng)MAC層功能，并與88E1111通過(guò)GMII接口實(shí)現(xiàn)了通信。簡(jiǎn)單介紹了程序頂層模塊的結(jié)構(gòu)以及各個(gè)子模塊的功能與實(shí)現(xiàn)方法，包括MAC模塊、時(shí)鐘產(chǎn)生模塊、數(shù)據(jù)緩存FIFO模塊等等。編譯代碼無(wú)誤后，結(jié)合modelsim對(duì)程序進(jìn)行了功能仿真，，驗(yàn)證了程序的正確性。最后，在PC機(jī)終端編寫(xiě)了基于WinPcap的VC++采集界面，對(duì)系統(tǒng)發(fā)送的數(shù)據(jù)包進(jìn)行抓取，實(shí)現(xiàn)FPGA與PC機(jī)的通信，并驗(yàn)證數(shù)據(jù)的正確性。對(duì)FPGA PHY端口送出的信號(hào)以及PC機(jī)采集到的信號(hào)數(shù)據(jù)進(jìn)行分析，表明系統(tǒng)實(shí)現(xiàn)了預(yù)定的功能且運(yùn)行穩(wěn)定。
[Abstract]:Optical fiber transmission uses the new generation of optical fiber as transmission medium, which has the advantages of high transmission speed, high data bandwidth, long transmission distance and low signal loss, etc. It is suitable for long-distance and high-speed transmission of large capacity data. And in terms of information transmission security, also higher than other transmission technology. With CCD or CMOS as imaging medium, digital camera can effectively convert optical signal into electrical signal, which is convenient for later transmission and processing, so it has been widely used. Ethernet technology has shown great vitality and great development from the beginning of its introduction. It becomes more and more attractive to use the advantage of Ethernet bandwidth to transmit high quality image data. Compared with Ethernet, the bandwidth of other transmission protocols is still relatively small, and the data transmission rate is relatively low, which can not meet the requirements of high quality image transmission. Ethernet technology can meet this requirement very well, realized the high-speed transmission of a lot of data. This paper uses gigabit fiber Ethernet to transmit digital camera data to obtain high-speed data transmission. At the same time, the Ethernet protocol is implemented by FPGA, which improves the portability and flexibility of the system, and brings convenience to the upgrade of the system in the future. This paper first introduces the working principle of digital camera and the theoretical basis of optical fiber transmission, then completes the design of the circuit board used in the system, and introduces the circuit schematic design method of each module of the circuit board. The principle and use of FPGA chip and physical layer chip 88E1111 are introduced, and the working mode of 88E1111 chip is configured by hardware configuration method. Thirdly, the function of Ethernet MAC layer based on VHDL language in FPGA is introduced, and the communication with 88E1111 through GMII interface is realized. This paper briefly introduces the structure of the top-level module of the program and the functions and implementation methods of each sub-module, including the MAC module, the clock generation module, the data cache FIFO module and so on. After compiling the code correctly, the program is simulated with modelsim to verify the correctness of the program. Finally, the VC acquisition interface based on WinPcap is written at the PC terminal, the data packet sent by the system is fetched, the communication between FPGA and PC is realized, and the correctness of the data is verified. By analyzing the signal from FPGA PHY port and the signal data collected by PC, it is shown that the system achieves the scheduled function and runs stably.
【學(xué)位授予單位】：中國(guó)科學(xué)院研究生院（西安光學(xué)精密機(jī)械研究所）
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TP393.11

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