發(fā)布時(shí)間：2018-05-30 20:32

  本文選題：CAN總線(xiàn) + 以太網(wǎng)��； 參考：《北京郵電大學(xué)》2014年碩士論文

【摘要】：將現(xiàn)場(chǎng)總線(xiàn)技術(shù)與以太網(wǎng)技術(shù)相結(jié)合是當(dāng)今工業(yè)控制領(lǐng)域的熱點(diǎn),現(xiàn)場(chǎng)總線(xiàn)的穩(wěn)定性實(shí)時(shí)性與以太網(wǎng)的靈活性都能得到體現(xiàn)。目前應(yīng)用最廣泛的現(xiàn)場(chǎng)總線(xiàn)是CAN總線(xiàn),CAN總線(xiàn)有成熟的國(guó)際標(biāo)準(zhǔn),被視為最有前途的現(xiàn)場(chǎng)總線(xiàn)之一。本文在Altera公司的FPGA平臺(tái)上,用RTL設(shè)計(jì)完成了CAN總線(xiàn)的軟核,方便進(jìn)行功能裁剪和移植,并通過(guò)配置Altera公司提供的三速以太網(wǎng)IP核(triple-speed-megacore)來(lái)實(shí)現(xiàn)以太網(wǎng)的協(xié)議,降低開(kāi)發(fā)成本,減少開(kāi)發(fā)周期,最后使用SDRAM轉(zhuǎn)存數(shù)據(jù)來(lái)實(shí)現(xiàn)兩個(gè)協(xié)議間的轉(zhuǎn)換。本文一共完成了以下幾個(gè)方面的工作： 1.完成了CAN協(xié)議的RTL設(shè)計(jì),包括讀寫(xiě)寄存器的設(shè)計(jì)、位同步設(shè)計(jì)、位流管理器設(shè)計(jì)。其中,讀寫(xiě)寄存器按照SJA1000的運(yùn)行機(jī)制來(lái)設(shè)計(jì),通過(guò)讀寫(xiě)寄存器來(lái)配置CAN總線(xiàn)的工作模式和波特率等；位同步設(shè)計(jì)中,用狀態(tài)機(jī)實(shí)現(xiàn)了同步段和相位緩沖段1,相位緩沖段2之間的跳轉(zhuǎn),從而完成了對(duì)采樣點(diǎn)和發(fā)送點(diǎn)的捕捉；位流管理器設(shè)計(jì)主要實(shí)現(xiàn)數(shù)據(jù)鏈路層的位編碼、CRC校驗(yàn)以及驗(yàn)收濾波的功能。每一部分都給出了仿真結(jié)果及詳細(xì)分析。 2.利用Altera公司提供的三速以太網(wǎng)IP核來(lái)實(shí)現(xiàn)以太網(wǎng)協(xié)議,本文詳細(xì)介紹了三速以太網(wǎng)IP核內(nèi)部的寄存器以及內(nèi)部FIFO,通過(guò)配置內(nèi)部的寄存器,來(lái)最終實(shí)現(xiàn)以太網(wǎng)的功能,詳細(xì)分析了以太網(wǎng)功能實(shí)現(xiàn)的仿真結(jié)果。除此之外,介紹了如何配置PHY端的接口,包括管理接口MDIO和數(shù)據(jù)接口,并用PHY芯片DP83658實(shí)現(xiàn)了以太網(wǎng)通信。 3.用SDRAM作為緩存數(shù)據(jù)的媒介來(lái)完成兩個(gè)協(xié)議的轉(zhuǎn)換。SDRAM的控制模塊分為狀態(tài)控制模塊、命令控制模塊和讀寫(xiě)控制模塊,其中狀態(tài)控制模塊主要實(shí)現(xiàn)控制SDRAM狀態(tài)的轉(zhuǎn)移,包括上電初始化和工作狀態(tài),工作狀態(tài)分為讀、寫(xiě)、自刷新等狀態(tài)。命令控制模塊實(shí)現(xiàn)對(duì)SDRAM的接口控制,通過(guò)接口信號(hào)控制SDRAM正常工作。讀寫(xiě)控制模塊,實(shí)現(xiàn)對(duì)SDRAM的讀寫(xiě)控制,與SDRAM進(jìn)行數(shù)據(jù)交換,本文詳細(xì)介紹了每個(gè)模塊的設(shè)計(jì),并分析了兩個(gè)協(xié)議轉(zhuǎn)換實(shí)現(xiàn)的波形仿真圖。 本論文實(shí)現(xiàn)了基于FPGA的CAN協(xié)議到以太網(wǎng)協(xié)議的轉(zhuǎn)換方案,在實(shí)際應(yīng)用中具有現(xiàn)實(shí)意義。
[Abstract]:The combination of fieldbus technology and Ethernet technology is a hot spot in the field of industrial control. The stability of fieldbus and the flexibility of Ethernet can be realized. At present, the most widely used fieldbus is CAN bus and can bus, which has mature international standard and is regarded as one of the most promising fieldbus. In this paper, the soft core of CAN bus is designed with RTL on the FPGA platform of Altera, which is convenient for function cutting and transplanting. The protocol of Ethernet is realized by configuring triple-speed-megacore, a three-speed Ethernet IP core provided by Altera, and the development cost is reduced. Reduce the development cycle, and finally use SDRAM to store data to achieve the conversion between the two protocols. This paper has completed the following aspects of work: 1. The RTL design of CAN protocol is completed, including the design of read and write register, bit synchronization and bit stream manager. The read and write register is designed according to the running mechanism of SJA1000, and the working mode and baud rate of the CAN bus are configured by the read and write register. The state machine is used to realize the jump between the synchronization segment and the phase buffer segment 1 and the phase buffer section 2, thus the capture of the sampling point and the transmitting point is completed. The design of bit stream manager mainly realizes the function of bit coding CRC check and acceptance filter in data link layer. The simulation results and detailed analysis are given in each part. 2. The Ethernet protocol is realized by using the three-speed Ethernet IP core provided by Altera Company. This paper introduces the register inside the three-speed Ethernet IP core and the internal FIFO in detail, and finally realizes the function of Ethernet by configuring the inner register. The simulation results of Ethernet function realization are analyzed in detail. In addition, this paper introduces how to configure the interface of PHY, including management interface MDIO and data interface, and realizes Ethernet communication with PHY chip DP83658. 3. The control module of SDRAM is divided into three modules: state control module, command control module and read and write control module, in which the state control module mainly controls the transfer of SDRAM state. Including power-on initialization and working state, working state is divided into read, write, self-refresh and so on. The command control module realizes the interface control of SDRAM, and controls the normal operation of SDRAM through interface signal. The read-write control module realizes the read / write control of SDRAM and the data exchange with SDRAM. This paper introduces the design of each module in detail, and analyzes the waveform simulation diagram of two protocol conversion implementation. This paper realizes the conversion scheme from CAN protocol to Ethernet protocol based on FPGA, which has practical significance in practical application.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TP273;TP393.11

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